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11. 发明授权

US5546807A High speed volumetric ultrasound imaging system 失效
标题翻译：高速体积超声成像系统
公开(公告)号：US5546807A
公开(公告)日：1996-08-20
申请号：US306716
申请日：1994-12-02
申请人： John T. Oxaal , Olaf T. Van Ramm , David M. Blaker , Robert S. Smith
发明人： John T. Oxaal , Olaf T. Van Ramm , David M. Blaker , Robert S. Smith
IPC分类号： G01N29/06 , G01S7/52 , G01S15/89
CPC分类号： G01S15/8993 , G01S7/52034 , G01S15/8925 , G01S15/8979 , G01S7/5206
摘要： A high speed method for presenting display of images obtained from a volumetric scanner in which multiple slices of object space are displayed simultaneously in real time thereby enabling a viewer to study relationships between various parts of the object. The slices are selectable by the viewer manipulating an icon on the display screen. Accordingly C-scans or B scans may be selected as well as I scans in which the scan plane has a selected orientation. Multiple I scans may be selected and viewed in perspective so that the viewer has an impression of a three dimensional display. Color and spectral doppler is incorporated with the scans to provide additional information of dynamic properties.
摘要翻译：用于呈现从体积扫描器获得的图像的显示的高速方法，其中实时地同时显示多个对象空间片段，从而使观众能够研究对象的各个部分之间的关系。切片可由观看者操纵显示屏上的图标来选择。因此，可以选择C扫描或B扫描以及扫描平面具有选定取向的I扫描。可以从透视图中选择和观看多个I扫描，使得观看者具有三维显示的印象。彩色和光谱多普勒与扫描并入，以提供动态属性的附加信息。

12. 发明授权

US5454014A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：US5454014A
公开(公告)日：1995-09-26
申请号：US152807
申请日：1993-11-16
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Mark E. Thierbach
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Mark E. Thierbach
IPC分类号： G06F17/10 , H03M13/41 , H04L27/00 , H03D1/00 , H04L27/06
CPC分类号： H03M13/6569 , G06F17/10 , H03M13/3961 , H03M13/41
摘要： A signal processor with an embedded Viterbi co-processor is disclosed. The Viterbi branch metric unit contains embedded metric units which calculate either Euclidean or Manhattan metrics for MLSE or deconvolution operations.
摘要翻译：公开了具有嵌入式维特比协处理器的信号处理器。维特比分支度量单位包含嵌入的度量单位，其计算用于MLSE或去卷积运算的欧几里德或曼哈顿度量。

13. 发明授权

US5559837A Efficient utilization of present state/next state registers 失效
公开(公告)号：US5559837A
公开(公告)日：1996-09-24
申请号：US488274
申请日：1995-06-07
申请人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
发明人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/45 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41
摘要： In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

14. 发明授权

US5550870A Viterbi processor 失效
标题翻译：维特比处理器
公开(公告)号：US5550870A
公开(公告)日：1996-08-27
申请号：US205961
申请日：1994-03-02
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
IPC分类号： H04L25/08 , H03M13/41 , H03M13/45 , H04L27/06
CPC分类号： H03M13/4169 , H03M13/3961 , H03M13/4138 , H03M13/6577 , H03M13/6591
摘要： A digital signal processor with an embedded error correcting coprocessor (ECCP) is disclosed. The ECCP provides soft symbol Viterbi decoded outputs which have the absolute value of the accumulated cost difference of competing states concatenated with the traceback bit or most significant bit of the next state.
摘要翻译：公开了一种具有嵌入式纠错协处理器（ECCP）的数字信号处理器。 ECCP提供软符号维特比解码输出，其具有与下一状态的追溯位或最高有效位连接的竞争状态的累积成本差的绝对值。

15. 发明授权

US5537445A Variable length tracebacks 失效
标题翻译：可变长度追溯
公开(公告)号：US5537445A
公开(公告)日：1996-07-16
申请号：US462459
申请日：1995-06-05
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H04L1/00 , H04L25/02 , H04L25/03 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6331 , H03M13/4169 , H04L25/03292 , H04L25/0242 , H04L25/025
摘要： A digital communication system including Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. The trellis of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. A second traceback is also initiated at the first symbol instant and traces a path back through the trellis a second predetermined number symbol instants to determine a second decoded symbol. The first traceback length may be greater than or less than the second traceback length. In another embodiment of the invention several tracebacks can be executed having a fixed traceback length, followed by other tracebacks having incrementally different traceback lengths. Such multiple tracebacks may be initiated in a single symbol instant. In yet another embodiment of the invention, selective ones of the decoded symbols are used by an equalizer to provide channel adaptation.
摘要翻译：公开了一种数字通信系统，包括维特比解码器，用于跟踪通过各种状态信息的网格的路径和操作方法。追溯确定解码的符号。幸存分支数据的网格存储在一组寄存器中。操作系统包括在第一个符号时刻从存储寄存器发起第一个追溯。回溯跟踪通过网格的路径返回第一预定数量的符号时刻以确定第一解码符号。第二追溯也在第一个符号时刻开始，并且通过网格追踪通过第二预定数字符号时刻的路径以确定第二解码符号。第一回溯长度可以大于或小于第二回溯长度。在本发明的另一个实施例中，可以执行具有固定回溯长度的几个回溯，随后是具有递增不同回溯长度的其他回溯。这样的多个回溯可以在单个符号瞬间启动。在本发明的另一个实施例中，均衡器使用解码符号中的选择性符号来提供信道适配。

16. 发明授权

US5533065A Decreasing length tracebacks 失效
标题翻译：减少长度回溯
公开(公告)号：US5533065A
公开(公告)日：1996-07-02
申请号：US174933
申请日：1993-12-28
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
IPC分类号： H04L27/00 , H03M13/23 , H03M13/41 , H04J3/00 , H04L1/00 , H04L27/06
CPC分类号： H03M13/3961 , H03M13/41 , H03M13/4169 , H04L1/0054
摘要： A communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A matrix of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. The length of the traceback is changed and another traceback is executed. This process is repeated until all remaining final decoded symbols are decoded. In an alternate embodiment, the traceback length is repreatedly decremented by one less than the constraint length, with each traceback obtaining multiple decoded symbols.
摘要翻译：公开了一种包括维特比解码器的通信系统，用于跟踪通过各种状态信息的网格和操作方法的路径。追溯确定解码的符号。幸存分支数据的矩阵存储在寄存器阵列中。操作系统包括在第一个符号时刻从存储寄存器发起第一个追溯。回溯跟踪通过网格的路径返回第一预定数量的符号时刻以确定第一解码符号。追溯的长度被更改，并且执行另一个追溯。重复该过程，直到所有剩余的最终解码符号被解码。在替代实施例中，回溯长度被重新递减一个小于约束长度，每个追溯获得多个解码符号。

17. 发明授权

US5513220A Digital receiver with minimum cost index register 失效
标题翻译：具有最小成本指数寄存器的数字接收器
公开(公告)号：US5513220A
公开(公告)日：1996-04-30
申请号：US152805
申请日：1993-11-16
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam
IPC分类号： H04L27/00 , H03M13/23 , H03M13/41 , H04L1/00 , H04L25/03 , H03D1/00 , H04L27/06
CPC分类号： H03M13/3961 , H03M13/41 , H03M13/4169 , H04L1/0054 , H04L25/03178
摘要： Convolutionally encoded information subjected to channel intersymbol interference is decoded by calculating the minimum cost path through a trellis. The trellis terminates in known states. Exploiting the open architecture of the coprocessor, the minimum cost state is checked to ascertain if it is the known, that is, correct state and if it is not, the possible known states are searched by the DSP inside the ECCP active register and the state with the lowest cost amont the possible states is selected.
摘要翻译：经由信道符号间干扰的卷积编码信息通过计算通过网格的最小成本路径被解码。网格在已知状态终止。利用协处理器的开放架构，检查最小成本状态以确定其是否已知，即正确状态，如果不是，那么可能的已知状态由ECCP活动寄存器内的DSP和状态选择最低的成本是不可能的状态。

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