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11. 发明申请

US20070057307A1 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US20070057307A1
公开(公告)日：2007-03-15
申请号：US11223235
申请日：2005-09-09
申请人： Danny Shum , Armin Tilke , Jiang Yan
发明人： Danny Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

12. 发明申请

US20070148921A1 Mixed orientation semiconductor device and method 有权
标题翻译：混合取向半导体器件及方法
公开(公告)号：US20070148921A1
公开(公告)日：2007-06-28
申请号：US11317737
申请日：2005-12-23
申请人： Jiang Yan , Danny Shum , Armin Tilke
发明人： Jiang Yan , Danny Shum , Armin Tilke
IPC分类号： H01L21/20 , H01L21/84 , H01L21/44
CPC分类号： H01L27/092 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
摘要翻译：制造半导体器件的方法从半导体晶片开始，半导体晶片包括覆盖第二半导体层的第一半导体层。在半导体晶片中蚀刻第一沟槽。第一个沟槽填充绝缘材料。在第一沟槽内蚀刻第二沟槽并穿过绝缘材料，使得绝缘材料沿着第一沟槽的侧壁保留。第二沟槽露出第二绝缘层的一部分。然后可以使用第二半导体层作为种子层在第二沟槽内生长半导体层。

13. 发明授权

US08319285B2 Silicon-on-insulator chip having multiple crystal orientations 有权
标题翻译：具有多个晶体取向的绝缘体上硅芯片
公开(公告)号：US08319285B2
公开(公告)日：2012-11-27
申请号：US11315069
申请日：2005-12-22
申请人： Armin Tilke , Jiang Yan , Matthias Hierlemann
发明人： Armin Tilke , Jiang Yan , Matthias Hierlemann
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/265 , H01L21/76 , H01L21/76251 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L29/7842 , H01L2924/0002 , H01L2924/00
摘要： A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.
摘要翻译：公开了具有多个晶体取向的绝缘体上硅器件。在一个实施例中，绝缘体上硅器件包括衬底层，设置在衬底层上的绝缘层，第一硅层和应变硅层。第一硅层具有第一晶体取向并且设置在绝缘层的一部分上，并且应变硅层设置在绝缘层的另一部分上并且具有不同于第一晶体取向的晶体取向。

14. 发明申请

US20070145481A1 Silicon-on-insulator chip having multiple crystal orientations 有权
标题翻译：具有多个晶体取向的绝缘体上硅芯片
公开(公告)号：US20070145481A1
公开(公告)日：2007-06-28
申请号：US11315069
申请日：2005-12-22
申请人： Armin Tilke , Jiang Yan , Matthias Hierlemann
发明人： Armin Tilke , Jiang Yan , Matthias Hierlemann
IPC分类号： H01L27/12
CPC分类号： H01L29/045 , H01L21/265 , H01L21/76 , H01L21/76251 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L29/7842 , H01L2924/0002 , H01L2924/00
摘要： A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.
摘要翻译：公开了具有多个晶体取向的绝缘体上硅器件。在一个实施例中，绝缘体上硅器件包括衬底层，设置在衬底层上的绝缘层，第一硅层和应变硅层。第一硅层具有第一晶体取向并且设置在绝缘层的一部分上，并且应变硅层设置在绝缘层的另一部分上并且具有不同于第一晶体取向的晶体取向。

15. 发明授权

US08115279B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08115279B2
公开(公告)日：2012-02-14
申请号：US12769271
申请日：2010-04-28
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/06
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

16. 发明授权

US07883987B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07883987B2
公开(公告)日：2011-02-08
申请号：US12762172
申请日：2010-04-16
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

17. 发明授权

US07749859B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07749859B2
公开(公告)日：2010-07-06
申请号：US11771583
申请日：2007-06-29
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/00
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

18. 发明授权

US07619310B2 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US07619310B2
公开(公告)日：2009-11-17
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

19. 发明申请

US20070059897A1 Isolation for semiconductor devices 审中-公开
标题翻译：半导体器件隔离
公开(公告)号：US20070059897A1
公开(公告)日：2007-03-15
申请号：US11223232
申请日：2005-09-09
申请人： Armin Tilke , Bee Hong
发明人： Armin Tilke , Bee Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/3065 , H01L21/3086
摘要： Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to further scale the size of semiconductor devices. A first etch process is used to form a first trench portion, and a second etch process or an oxidation process is used to form a second trench portion beneath the first trench portion. The second trench portion is wider than the first trench portion. A liner may form during the first trench portion on the sidewalls of the first trench portion that protects the first trench portion sidewalls during the second etch process, in one embodiment. Alternatively, a liner may be deposited on the sidewalls of the first trench portion, in another embodiment.
摘要翻译：公开了用于半导体器件的隔离结构的形成方法和结构。隔离结构在底部比在顶部更宽，提供了进一步缩小半导体器件尺寸的能力。第一蚀刻工艺用于形成第一沟槽部分，并且第二蚀刻工艺或氧化工艺用于在第一沟槽部分下方形成第二沟槽部分。第二沟槽部分比第一沟槽部分宽。在一个实施例中，衬垫可以在第一沟槽部分的侧壁处的第一沟槽部分期间形成，其在第二蚀刻工艺期间保护第一沟槽部分侧壁。或者，在另一个实施例中，衬垫可以沉积在第一沟槽部分的侧壁上。

20. 发明授权

US07858964B2 Semiconductor device formed in a recrystallized layer 有权
标题翻译：半导体器件形成在再结晶层中
公开(公告)号：US07858964B2
公开(公告)日：2010-12-28
申请号：US12368122
申请日：2009-02-09
申请人： Roman Knoefler , Armin Tilke
发明人： Roman Knoefler , Armin Tilke
IPC分类号： H01L31/00 , H01L29/00 , H01L27/108
CPC分类号： H01L21/823807 , H01L21/26506 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel.
摘要翻译：半导体器件包括在第一层上包括第一层和再结晶层的衬底。第一层具有第一固有应力，再结晶层具有第二固有应力。在再结晶层中形成晶体管。晶体管包括源极区域，漏极区域和源极和漏极区域之间的电荷载流子通道。第二本征应力基本上平行于电荷载流子通道排列。

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