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11. 再颁专利

USRE41021E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41021E1
公开(公告)日：2009-12-01
申请号：US11451588
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

12. 再颁专利

USRE41019E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41019E1
公开(公告)日：2009-12-01
申请号：US11451589
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

13. 发明授权

US5949714A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5949714A
公开(公告)日：1999-09-07
申请号：US190459
申请日：1998-11-13
申请人： Gertjan Hemink , Tomoharu Tanaka
发明人： Gertjan Hemink , Tomoharu Tanaka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/12 , G11C16/3454 , H01L29/7881
摘要： In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.
摘要翻译：在包括以矩阵方式布置获得的电可编程存储单元的非易失性半导体存储器件中，每个存储单元包括通过绝缘膜在半导体层上层叠电荷存储层和控制栅极，阈值电压在擦除后检测存储单元，并且数据在相对低电压的快速可编程单元中编程，并且在相对较高的电压下被编程在慢可编程单元中，从而在编程时间内在编程之后抑制阈值电压的变化。

14. 发明授权

US5555204A Non-volatile semiconductor memory device 失效
标题翻译： Eeprom用于使用隧道电流写入和擦除数据。
公开(公告)号：US5555204A
公开(公告)日：1996-09-10
申请号：US266633
申请日：1994-06-28
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C16/02
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

15. 发明授权

US5521865A Non-volatile semiconductor memory device for storing multi-value data 失效
标题翻译：用于存储多值数据的非易失性半导体存储器件
公开(公告)号：US5521865A
公开(公告)日：1996-05-28
申请号：US401789
申请日：1995-03-10
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Gertjan Hemink
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5642
摘要： A non-volatile semiconductor memory device having a plurality of electrically rewritable memory cells for storing multi-value data. The cells are arranged in an array and are coupled to a plurality of bit lines which transmit and receive data to and from the memory cells. The device also includes a plurality of sense amplifiers for sensing and amplifying the potentials of the bit lines; a plurality of data latches forming data to be written in the memory cells; a plurality of verify circuits for checking whether the data is correctly written in the memory cells and a plurality of switches. The switches control the connections of the sense amplifiers, data latches and verify circuits to the bit lines. Write control devices set the potentials of the bit lines in accordance with the contents of the data latches. The switches are set in an open state after data is read from the memory cells onto the bit lines and the sense amplifiers almost simultaneously operate after the switches are set in an open state to sense and amplify the data read onto the bit lines.
摘要翻译：一种具有用于存储多值数据的多个电可重写存储单元的非易失性半导体存储器件。单元被布置成阵列并且耦合到多个位线，其向存储器单元发送数据和从存储器单元接收数据。该器件还包括多个读出放大器，用于感测和放大位线的电位; 多个数据锁存器，形成要写入存储单元的数据; 用于检查数据是否正确写入存储单元的多个验证电路和多个开关。开关控制读出放大器，数据锁存器和验证电路到位线的连接。写控制装置根据数据锁存器的内容设置位线的电位。在将数据从存储器单元读取到位线上之后，开关被设置为打开状态，并且在开关被设置为打开状态之后，读出放大器几乎同时工作，以感测和放大读取到位线上的数据。

16. 发明授权

US6014330A Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6014330A
公开(公告)日：2000-01-11
申请号：US167969
申请日：1998-10-08
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

17. 发明授权

US5870334A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5870334A
公开(公告)日：1999-02-09
申请号：US873015
申请日：1997-06-11
申请人： Gertjan Hemink , Tomoharu Tanaka
发明人： Gertjan Hemink , Tomoharu Tanaka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/12 , G11C16/3454 , H01L29/7881
摘要： In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.

18. 发明授权

US5774397A Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state 失效
标题翻译：非易失性半导体存储器件以及将非易失性存储器单元编程到预定状态的方法
公开(公告)号：US5774397A
公开(公告)日：1998-06-30
申请号：US711652
申请日：1996-09-10
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

19. 再颁专利

USRE41244E1 Multi-state EEPROM having write-verify control circuit 有权
标题翻译：具有写入验证控制电路的多状态EEPROM
公开(公告)号：USRE41244E1
公开(公告)日：2010-04-20
申请号：US11451585
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.
摘要翻译：一种具有存储单元阵列的EEPROM，其中电可编程存储器单元以矩阵形式布置，并且每个存储单元具有三个存储状态，包括用于临时存储用于控制多个存储单元的写入操作状态的数据的多个数据电路，用于根据分别对应于存储单元的数据电路的内容执行写入操作的写入电路，用于确认在写入操作时设置的存储单元的状态的写入验证电路，以及用于更新基于数据电路的内容和在写入操作时设置的存储单元的状态，仅对仅写入数据的存储单元执行重写操作的数据电路的内容。重复执行基于数据电路的内容的写入操作，写入验证操作和数据电路内容更新操作，直到存储器单元被设置为预定的写入状态。

20. 发明授权

US07035146B2 Programming non-volatile memory 有权
标题翻译：编程非易失性存储器
公开(公告)号：US07035146B2
公开(公告)日：2006-04-25
申请号：US11081134
申请日：2005-03-15
申请人： Gertjan Hemink , Yupin Fong
发明人： Gertjan Hemink , Yupin Fong
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage element have reached an intermediate verify threshold but have not reached a final verify threshold. One additional programming operation at a reduced level is performed for the non-volatile storage elements that have reached the intermediate verify threshold but have not reached the final verify threshold, and those non-volatile storage elements are then inhibited from further programming. Non-volatile storage elements that have not reached the intermediate verify threshold continue programming. Non-volatile storage elements that reach the final verify threshold are inhibited from programming.
摘要翻译：对一组非易失性存储元件执行一个或多个编程操作。例如，编程操作可以包括应用一组编程脉冲。执行验证过程以确定哪个非易失性存储元件已经达到中间验证阈值但尚未达到最终验证阈值。对于已经达到中间验证阈值但尚未达到最终验证阈值的非易失性存储元件执行降级的一个附加编程操作，然后禁止那些非易失性存储元件进一步编程。未达到中间验证阈值的非易失性存储元件继续编程。达到最终验证阈值的非易失性存储元件被禁止编程。

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