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11. 发明授权

US06597605B2 Systems with non-volatile memory bit sequence program control 有权
标题翻译：具有非易失性存储器位序列程序控制的系统
公开(公告)号：US06597605B2
公开(公告)日：2003-07-22
申请号：US10139057
申请日：2002-05-03
申请人： Jerry A. Kreifels , Rodney R. Rozman
发明人： Jerry A. Kreifels , Rodney R. Rozman
IPC分类号： G11C700
CPC分类号： G11C16/10 , G11C16/3454
摘要： Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.
摘要翻译：包括位序列程序控制器的系统，用于在可编程非易失性存储器单元阵列中对序列中的非易失性存储单元进行编程。比特序列程序控制器通过将程序字的位与可编程非易失性存储单元的阵列的擦除逻辑状态进行比较来确定需要编程的位。比特序列程序控制器进一步指示非易失性存储器单元阵列中的非易失性存储单元的单词中的哪些非易失性存储单元需要编程以匹配程序字。比特序列程序控制器通过对不在擦除逻辑状态的程序字的位数进行计数来确定程序字中编程的位数，来确定编程应该何时完成。

12. 发明授权

US06418059B1 Method and apparatus for non-volatile memory bit sequence program controller 有权
标题翻译：用于非易失性存储器位序列程序控制器的方法和装置
公开(公告)号：US06418059B1
公开(公告)日：2002-07-09
申请号：US09603671
申请日：2000-06-26
申请人： Jerry A. Kreifels , Rodney R. Rozman
发明人： Jerry A. Kreifels , Rodney R. Rozman
IPC分类号： G11C700
CPC分类号： G11C16/10 , G11C16/3454
摘要： A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.
摘要翻译：一种位序列程序控制器，用于对可编程非易失性存储单元阵列中的非易失性存储器单元进行编程。比特序列程序控制器通过将程序字的位与可编程非易失性存储单元的阵列的擦除逻辑状态进行比较来确定需要编程的位。比特序列程序控制器进一步指示非易失性存储器单元阵列中的非易失性存储单元的单词中的哪些非易失性存储单元需要编程以匹配程序字。比特序列程序控制器通过对不在擦除逻辑状态的程序字的位数进行计数来确定程序字中编程的位数来确定编程应该何时完成，从而对需要编程的位数进行计数。

13. 发明授权

US5526311A Method and circuitry for enabling and permanently disabling test mode access in a flash memory device 失效
标题翻译：用于启用和永久禁用闪存设备中测试模式访问的方法和电路
公开(公告)号：US5526311A
公开(公告)日：1996-06-11
申请号：US175599
申请日：1993-12-30
申请人： Jerry A. Kreifels , Richard J. Durante , Alexander C. Mitchell, III
发明人： Jerry A. Kreifels , Richard J. Durante , Alexander C. Mitchell, III
IPC分类号： G01R31/317 , G11C29/46 , G11C29/00
CPC分类号： G01R31/31701 , G11C29/46
摘要： A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of "keys" are presented in the proper sequence via the memory device pins. During the first phase of the unlocking process, an array controller determines whether the correct confirmation codes were input via the address and data pins. If they were, the array controller proceeds to the second phase of the unlocking process. During the second phase voltage levels on selected control pins are checked for a transition to a first voltage level. If the control pins transition as required, the array controller proceeds to the third phase. During the third phase, the array controller waits a limited time for receipt of a second test mode enable command. The second test mode enable command must be followed by correct confirmation codes. If the third phase is successfully completed, the array controller writes to a test mode enable access register. As a result, an enable test mode signal becomes active, which allows the user interlace to respond to subsequently issued test mode commands. Also described is a method of eliminating access to the test mode of the semiconductor memory device, which includes a nonvolatile instruction memory.
摘要翻译：一种能够响应于用户命令访问半导体存储器的测试模式的方法。该方法仅在通过存储器件引脚以适当顺序呈现多个“键”时才允许测试模式访问。在解锁过程的第一阶段，阵列控制器确定是否通过地址和数据引脚输入了正确的确认码。如果是，阵列控制器进入解锁过程的第二阶段。在第二阶段期间，检查所选择的控制引脚上的电压电平以转换到第一电压电平。如果控制引脚根据需要进行转换，则阵列控制器进入第三阶段。在第三阶段期间，阵列控制器等待有限的时间接收第二测试模式使能命令。第二个测试模式使能命令必须遵循正确的确认代码。如果第三阶段成功完成，阵列控制器写入测试模式使能访问寄存器。因此，使能测试模式信号变为有效，这允许用户交织响应随后发出的测试模式命令。还描述了一种消除对包括非易失性指令存储器的半导体存储器件的测试模式的访问的方法。

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