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11. 发明授权

US06525737B1 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06525737B1
公开(公告)日：2003-02-25
申请号：US09378439
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元从多边形存储器接收输入并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

12. 发明授权

US06614444B1 Apparatus and method for fragment operations in a 3D-graphics pipeline 有权
标题翻译： 3D图形管道中的碎片操作的装置和方法
公开(公告)号：US06614444B1
公开(公告)日：2003-09-02
申请号：US09372137
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Sushma S. Trivedi , Sam Ng , Lindy Fung , Richard E. Hessel , Jack Benkual
发明人： Jerome F. Duluk, Jr. , Sushma S. Trivedi , Sam Ng , Lindy Fung , Richard E. Hessel , Jack Benkual
IPC分类号： G09G500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a stage for performing a fragment operation on a fragment on a per-pixel basis, as well as a stage for performing a fragment operation on the fragment on a per-sample basis. The stage for performing on a per-pixel basis is one of the following: a scissor-test stage, a stipple-test stage, an alpha-test stage or a colorest stage, and the stage for performing on a per-sample basis is one of the following: a Z-test stage, a blending stage or a dithering stage. The apparatus programmatically selects whether to perform a stencil test on a per-pixel or a per-sample basis and performs the stencil test on the selected basis. The apparatus also programmatically selects pixel samples for per-sample operations, where the sample selections differ with different instances of the same per-sample operation. The apparatus also programmatically selects a set of subdivisions of a pixel as samples for use in the per-sample fragment operation, programmatically assigns different weights to at least two samples in the set and performs the per-sample fragments operation on the fragment using the programmatically selected and differently weighted samples.
摘要翻译：用于渲染3D图形图像的装置和方法。该装置包括用于从图形应用程序接收命令的端口，用于将呈现的图像发送到显示器的输出端和耦合到端口和输出端的分段操作流水线，流水线包括用于执行片段操作的级基于每个像素的片段，以及在每个样本的基础上对片段执行片段操作的阶段。基于每像素执行的阶段是以下之一：剪刀测试阶段，点测试阶段，α测试阶段或阶段阶段，以及每个采样基础执行的阶段是以下之一：Z测试阶段，混合阶段或抖动阶段。该设备以编程方式选择是在每个像素还是每个样本的基础上执行模板测试，并在所选择的基础上执行模板测试。该设备还以编程方式选择每采样操作的像素采样，其中样本选择与相同每采样操作的不同实例不同。该装置还以编程方式选择一组像素的细分作为在每个样本片段操作中使用的样本，以编程方式向集合中的至少两个样本分配不同的权重，并使用编程方式对该片段执行每个样本片段的操作选择和不同加权的样本。

13. 发明授权

US06693639B2 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06693639B2
公开(公告)日：2004-02-17
申请号：US10290414
申请日：2002-11-07
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元接收来自多边形存储器的输入，并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

14. 发明授权

US07164426B1 Method and apparatus for generating texture 有权
标题翻译：用于产生纹理的方法和装置
公开(公告)号：US07164426B1
公开(公告)日：2007-01-16
申请号：US09724663
申请日：2000-11-28
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
IPC分类号： G06F12/00 , G06F12/02 , G06T11/40
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译：一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

15. 发明授权

US06288730B1 Method and apparatus for generating texture 有权
标题翻译：用于产生纹理的方法和装置
公开(公告)号：US06288730B1
公开(公告)日：2001-09-11
申请号：US09378408
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
IPC分类号： G06T1140
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译：一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

16. 发明授权

US06577317B1 Apparatus and method for geometry operations in a 3D-graphics pipeline 有权
标题翻译： 3D图形流水线中几何运算的装置和方法
公开(公告)号：US06577317B1
公开(公告)日：2003-06-10
申请号：US09379144
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Vaughn T. Arnold , Tuan D. Nguyen , Richard E. Hessel , Stephen L. Dodgen , Shun Wai Go
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Vaughn T. Arnold , Tuan D. Nguyen , Richard E. Hessel , Stephen L. Dodgen , Shun Wai Go
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T15/005 , G06T15/30 , G06T15/50
摘要： An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.
摘要翻译：用于渲染3D图形图像的装置和方法优选地包括用于从图形应用程序接收命令的端口，用于将呈现的图像发送到显示器的输出和耦合到端口和输出的几何运算流水线，几何形状操作流程包括用于执行转换的块。在一个实施例中，用于执行变换的块包括共同扩展的逻辑和第一物理级，以及包括多个逻辑级的第二物理级。第二个物理阶段包括交错执行的多个逻辑阶段。

17. 发明授权

US5499356A Method and apparatus for a multiprocessor resource lockout instruction 失效
标题翻译：多处理器资源锁定指令的方法和装置
公开(公告)号：US5499356A
公开(公告)日：1996-03-12
申请号：US173923
申请日：1993-12-28
申请人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
发明人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F12/14
CPC分类号： G06F15/8076 , G06F15/17381 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30069 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/526 , G06F2209/521
摘要： A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.
摘要翻译：一种用于在共享存储器中提供资源锁定机制的方法和装置，该多处理器系统能够在同一存储器操作期间同时执行读取和写入操作。本发明的加载和标志指令可以在相同的存储器操作期间执行读取操作，随后将预选标志值写入同一个存储器位置。加载和标志指令特别适用于在蒙特卡罗应用程序中使用的资源锁定机制。

18. 发明授权

US06195676B1 Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes 失效
标题翻译：用于实现进程分配调度的多处理器操作系统程序中用户端调度的方法和装置
公开(公告)号：US06195676B1
公开(公告)日：2001-02-27
申请号：US08003000
申请日：1993-01-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F946
CPC分类号： G06F9/30149 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

19. 发明授权

US5179702A System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling 失效
标题翻译：用于使用基于无政府状态的调度器来控制并行执行线程调度的高度并行多处理器的系统和方法
公开(公告)号：US5179702A
公开(公告)日：1993-01-12
申请号：US537466
申请日：1990-06-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F9/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F9/48 , G06F11/28 , G06F11/36 , G06F12/02 , G06F12/08 , G06F12/12 , G06F15/16 , G06F15/167 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F9/30149 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

20. 发明授权

US06771264B1 Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor 有权
标题翻译：在延迟着色图形处理器中执行切线空间照明和凹凸贴图的方法和装置
公开(公告)号：US06771264B1
公开(公告)日：2004-08-03
申请号：US09213990
申请日：1999-12-17
申请人： Jerome F. Duluk , Stephen L. Dodgen , Joseph P. Bratt , Matthew Papakipos , Nathan Tuck , Richard E. Hessel
发明人： Jerome F. Duluk , Stephen L. Dodgen , Joseph P. Bratt , Matthew Papakipos , Nathan Tuck , Richard E. Hessel
IPC分类号： G06T1560
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (vs, vt, n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor. The Phong shader performs all lighting computations in eye space, which requires it first to transform bump data from tangent space to eye space. In one embodiment the Phong hardware does this by multiplying a matrix M whose columns comprise eye space basis vectors (bs, bt, n) derived from the surface basis vectors (vs, vt, n) and the vector Tb of bump map data. The eye space basis vectors are derived by the DSGP preprocessor so that the multiplication (M×Tb) gives the perturbed surface normal N′ in eye space, reflecting the bump effects. The perturbed surface normal N′ is subsequently used in the lighting computations.
摘要翻译：用于在延迟着色图形处理器（DSGP）中执行切线空间照明的系统和方法包括预处理数据的DSGP的块和仅在所有片段被预处理之后才执行的Phong着色器。预处理器块接收以各种格式指定的纹理贴图，并将这些纹理贴图转换为普通格式供Phong着色器使用。预处理器块为Phong着色器提供了内插表面基向量（vs，vt，n），一个向量Tb，它在切向/对象空间中表示纹理贴图中的纹理/凹凸数据，光数据，材料数据，眼睛坐标等 Phong着色器使用的信息执行照明和凹凸贴图计算。为需要计算照明效果的每个片段提供来自预处理器的数据。 Phong着色器使用预处理器提供的信息计算片段的颜色。 Phong着色器执行眼睛空间中的所有照明计算，这需要它首先将凹凸数据从切线空间转换为眼睛空间。在一个实施例中，Phong硬件通过乘以其列包括从表面基矢量（vs，vt，n）导出的凹凸贴图数据的矢量Tb的基准矢量（bs，bt，n）的矩阵M来实现。通过DSGP预处理器导出眼空间基矢量，使得乘法（MxTb）给出了眼空间中的扰动表面法线N'，反映了碰撞效应。扰动表面法线N'随后用于照明计算。

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