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11. 发明申请

US20120273802A1 JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY 有权
标题翻译：具有电流冲击能力的接线棒肖特基二极管
公开(公告)号：US20120273802A1
公开(公告)日：2012-11-01
申请号：US13547014
申请日：2012-07-11
申请人： Qingchun Zhang , Sei-Hyung Ryu
发明人： Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L29/24
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/1608 , H01L29/47 , H01L29/861
摘要： An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.
摘要翻译：电子器件包括具有第一导电类型的碳化硅漂移区，漂移区上的肖特基接触以及与肖特基接触相邻的漂移区的表面处的多个接合势垒肖特基（JBS）区。 JBS区域具有与第一导电类型相反的第二导电类型，并且在相邻的JBS区域之间具有第一间隔。该装置还包括具有第二导电类型的多个浪涌保护子区域。浪涌保护子区域中的每一个在相邻的浪涌保护子区域之间具有小于第一间隔的第二间隔。

12. 发明申请

US20110049561A1 Solid-State Pinch Off Thyristor Circuits 有权
标题翻译：固态闭合晶闸管电路
公开(公告)号：US20110049561A1
公开(公告)日：2011-03-03
申请号：US12550574
申请日：2009-08-31
申请人： Robert J. Callanan , Sei-Hyung Ryu , Qingchun Zhang
发明人： Robert J. Callanan , Sei-Hyung Ryu , Qingchun Zhang
IPC分类号： H01L29/74 , H01L29/744
CPC分类号： H01L29/745 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/7455
摘要： Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.
摘要翻译：提供了一种半导体双稳态开关器件，其包括包括阳极层，漂移层，栅极层和阴极层的晶闸管部分，栅极层可操作以接收栅极触发电流，当阳极层相对于阴极层使晶闸管部分锁定在阳极和阴极之间的导电模式。器件还包括形成在晶闸管部分上的晶体管部分，晶体管部分包括源极，漏极和晶体管栅极，漏极耦合到晶闸管部分的阴极。

13. 发明授权

US07883949B2 Methods of forming silicon carbide switching devices including P-type channels 有权
标题翻译：形成包括P型通道的碳化硅切换装置的方法
公开(公告)号：US07883949B2
公开(公告)日：2011-02-08
申请号：US11740687
申请日：2007-04-26
申请人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
发明人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L21/337
CPC分类号： H01L21/324 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7838 , Y10S438/931
摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.
摘要翻译：在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域并且在邻近p型区域的n型阱中至少部分地限定沟道区。在通道区域中形成阈值调整区域。注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道邻近p型区域的n型阱区域。阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

14. 发明申请

US20080029838A1 Semiconductor devices including Schottky diodes with controlled breakdown and methods of fabricating same 有权
标题翻译：包括具有受控击穿的肖特基二极管的半导体器件及其制造方法
公开(公告)号：US20080029838A1
公开(公告)日：2008-02-07
申请号：US11496842
申请日：2006-08-01
申请人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
发明人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L29/47
CPC分类号： H01L29/0619 , H01L21/046 , H01L29/0615 , H01L29/1608 , H01L29/6606 , H01L29/872
摘要： A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.
摘要翻译：半导体器件包括具有第一导电类型的半导体层，半导体层上的金属接触并与半导体层形成肖特基结，以及半导体层中的半导体区域。半导体区域和半导体层与肖特基结并联形成第一p-n结。第一p-n结被配置为当肖特基结被反向偏置时在与肖特基结相邻的半导体层中产生耗尽区，从而限制通过肖特基结的反向漏电流。第一p-n结进一步配置成使得当肖特基结被反向偏置时，第一p-n结的穿通以比肖特基结的击穿电压低的电压发生。

15. 发明授权

US08803277B2 Junction termination structures including guard ring extensions and methods of fabricating electronic devices incorporating same 有权
标题翻译：接线端接结构包括保护环延伸件和制造并入其的电子器件的方法
公开(公告)号：US08803277B2
公开(公告)日：2014-08-12
申请号：US13024812
申请日：2011-02-10
申请人： Jason Henning , Qingchun Zhang , Sei-Hyung Ryu
发明人： Jason Henning , Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L29/38
CPC分类号： H01L29/0619 , H01L29/045 , H01L29/0615 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.
摘要翻译：电子器件包括半导体层，半导体层中的主结，围绕初级结的轻掺杂区和与初级结相邻的轻掺杂区中的结端接结构。接合端接结构具有上边界和边界以及上边界和边界之间的拐角，并且轻掺杂区域在远离主结点的第一方向上延伸并垂直于上边界上的一点，由小于第二距离的第一距离，通过该第二距离，轻掺杂区域在远离主结点的第二方向上延伸并且垂直于拐角处的点。至少一个浮动保护环段可以设置在接合端接结构的拐角外的半导体层中。还公开了相关方法。

16. 发明授权

US07728402B2 Semiconductor devices including schottky diodes with controlled breakdown 有权
标题翻译：半导体器件包括具有受控击穿的肖特基二极管
公开(公告)号：US07728402B2
公开(公告)日：2010-06-01
申请号：US11496842
申请日：2006-08-01
申请人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
发明人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07
CPC分类号： H01L29/0619 , H01L21/046 , H01L29/0615 , H01L29/1608 , H01L29/6606 , H01L29/872
摘要： A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.
摘要翻译：半导体器件包括具有第一导电类型的半导体层，半导体层上的金属接触并与半导体层形成肖特基结，以及半导体层中的半导体区域。半导体区域和半导体层与肖特基结并联形成第一p-n结。第一p-n结被配置为当肖特基结被反向偏置时在与肖特基结相邻的半导体层中产生耗尽区，从而限制通过肖特基结的反向漏电流。第一p-n结进一步配置成使得当肖特基结被反向偏置时，第一p-n结的穿通以比肖特基结的击穿电压低的电压发生。

17. 发明申请

US20090289262A1 JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY 有权
标题翻译：具有电流冲击能力的接线棒肖特基二极管
公开(公告)号：US20090289262A1
公开(公告)日：2009-11-26
申请号：US12124341
申请日：2008-05-21
申请人： Qingchun Zhang , Sei-Hyung Ryu
发明人： Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L29/24 , H01L21/04
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/1608 , H01L29/47 , H01L29/861
摘要： An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.
摘要翻译：电子器件包括具有第一导电类型的碳化硅漂移区，漂移区上的肖特基接触以及与肖特基接触相邻的漂移区的表面处的多个接合势垒肖特基（JBS）区。 JBS区域具有与第一导电类型相反的第二导电类型，并且在相邻的JBS区域之间具有第一间隔。该装置还包括具有第二导电类型的多个浪涌保护子区域。浪涌保护子区域中的每一个在相邻的浪涌保护子区域之间具有小于第一间隔的第二间隔。

18. 发明授权

US08354690B2 Solid-state pinch off thyristor circuits 有权
标题翻译：固态夹断晶闸管电路
公开(公告)号：US08354690B2
公开(公告)日：2013-01-15
申请号：US12550574
申请日：2009-08-31
申请人： Robert J. Callanan , Sei-Hyung Ryu , Qingchun Zhang
发明人： Robert J. Callanan , Sei-Hyung Ryu , Qingchun Zhang
IPC分类号： H01L29/74
CPC分类号： H01L29/745 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/7455
摘要： Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.
摘要翻译：提供了一种半导体双稳态开关器件，其包括包括阳极层，漂移层，栅极层和阴极层的晶闸管部分，栅极层可操作以接收栅极触发电流，当阳极层相对于阴极层使晶闸管部分锁定在阳极和阴极之间的导电模式。器件还包括形成在晶闸管部分上的晶体管部分，晶体管部分包括源极，漏极和晶体管栅极，漏极耦合到晶闸管部分的阴极。

19. 发明授权

US08193848B2 Power switching devices having controllable surge current capabilities 有权
标题翻译：功率开关器件具有可控的浪涌电流能力
公开(公告)号：US08193848B2
公开(公告)日：2012-06-05
申请号：US12610582
申请日：2009-11-02
申请人： Qingchun Zhang , James Theodore Richmond , Anant K. Agarwal , Sei-Hyung Ryu
发明人： Qingchun Zhang , James Theodore Richmond , Anant K. Agarwal , Sei-Hyung Ryu
IPC分类号： H03K5/08
CPC分类号： H01L29/7302 , H01L21/8213 , H01L25/072 , H01L25/18 , H01L27/0605 , H01L27/0705 , H01L27/088 , H01L29/1608 , H01L29/739 , H01L29/7803 , H01L2224/04042 , H01L2224/06181 , H01L2224/48137 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide band-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.
摘要翻译：半导体开关器件包括宽带隙功率晶体管，与功率晶体管并联耦合的宽带隙浪涌电流晶体管，以及被配置为驱动浪涌电流晶体管的宽带隙驱动晶体管。当功率晶体管的漏极 - 源极电压处于第一电压范围内时，半导体开关器件的大部分导通状态输出电流流过功率晶体管的沟道，该范围可以例如对应于漏极在正常运行期间预期的电源电压。相比之下，半导体开关器件被进一步配置成使得在导通状态下，当功率晶体管的漏 - 源电压在一秒内时，输出电流流过功率晶体管的浪涌电流晶体管和沟道，电压范围

20. 发明申请

US20110121318A1 Silicon Carbide Switching Devices Including P-Type Channels 有权
标题翻译：包括P型通道的碳化硅切换装置
公开(公告)号：US20110121318A1
公开(公告)日：2011-05-26
申请号：US13019723
申请日：2011-02-02
申请人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
发明人： Mrinal Kanti Das , Qingchun Zhang , Sei-Hyung Ryu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/324 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7838 , Y10S438/931
摘要： Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×1016 cm−3 to about 5×1018 cm−3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm2/V-s at a gate voltage of −25V.
摘要翻译：在碳化硅中形成p沟道MOS器件的方法包括在碳化硅层中形成n型阱，以及注入p型掺杂离子以在n型阱的表面形成p型区域并且在邻近p型区域的n型阱中至少部分地限定沟道区。在通道区域中形成阈值调整区域。注入的离子在惰性气氛中在大于1650℃的温度下进行退火。在沟道区上形成栅极氧化层，栅极氧化层上形成栅极。基于碳化硅的晶体管包括碳化硅层，碳化硅层中的n型阱以及在碳化硅层的表面处的n型阱中的p型区域，并且至少部分地限定沟道邻近p型区域的n型阱区域。阈值调整区域在通道区域中，并且包括掺杂剂浓度为约1×10 16 cm -3至约5×10 18 cm -3的p型掺杂剂。晶体管还包括在沟道区上的栅极氧化层和栅极氧化物层上的栅极。晶体管可以在-25V的栅极电压下在沟道区中表现出超过5cm 2 / V-s的空穴迁移率。

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