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11. 发明授权

US08301907B2 Supporting advanced RAS features in a secured computing system 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US08301907B2
公开(公告)日：2012-10-30
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F11/30
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

12. 发明申请

US20090089566A1 SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US20090089566A1
公开(公告)日：2009-04-02
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

13. 发明申请

US20070041405A1 Method and system for response determinism by synchronization 有权
标题翻译：通过同步的响应确定性的方法和系统
公开(公告)号：US20070041405A1
公开(公告)日：2007-02-22
申请号：US11166030
申请日：2005-06-23
申请人： Muraleedhara Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris Matthews , Chris Gianos , Rahul Shah , Theodore Schoenborn
发明人： Muraleedhara Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris Matthews , Chris Gianos , Rahul Shah , Theodore Schoenborn
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/0041
摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.
摘要翻译：关于改进对测试矢量的集成设备确定性响应的讨论。例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。

14. 发明申请

US20060225074A1 Method and apparatus for communication between two or more processing elements 失效
标题翻译：用于在两个或多个处理元件之间进行通信的方法和装置
公开(公告)号：US20060225074A1
公开(公告)日：2006-10-05
申请号：US11095341
申请日：2005-03-30
申请人： Kushagra Vaid , John Crawford , Allen Baum
发明人： Kushagra Vaid , John Crawford , Allen Baum
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/522
摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.
摘要翻译：一种用于在多个程序线程之间执行屏障同步的技术。更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。

15. 发明授权

US4947364A Method in a computing system for performing a multiplication 失效
标题翻译：用于执行乘法的计算系统中的方法
公开(公告)号：US4947364A
公开(公告)日：1990-08-07
申请号：US392177
申请日：1989-08-09
申请人： Michael J. Mahon , Allen Baum
发明人： Michael J. Mahon , Allen Baum
IPC分类号： G06F7/52
CPC分类号： G06F7/5332
摘要： In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit. Second, for every other bit in the current section that is a "1", a shift-and-add operation is performed by shifting, via the preshifter, the contents of the first register by an amount equal to the number of bit places the bit is to the left of the low order bit of the current section and by adding, via the arithmetic logic unit, the preshifted contents of the first register to the contents of the second register. Third, for every section from the plurality of sections that does not contain low order bits of the first multiplicand, the contents of the first register "n" bits are shifted to the left.
摘要翻译：在计算系统中，呈现执行第一被乘数和第二被乘数相乘的方法。计算系统包括多个寄存器，指令解码器，算术逻辑单元和预定机。第一被乘数被分成多个等长的部分。每个部分包括“n”位，其中“n”是大于1的整数。第二被乘数被放置在来自多个寄存器的第一寄存器中。来自多个寄存器的第二寄存器被清零。对于来自多个部分的每个部分，从包含第一乘法的高阶位的第一部分开始，并且进行到包含第一被乘数的低阶位的第一被乘数的最后部分以及以下三个子步骤。首先，当当前部分的低位位为“1”时，第一寄存器的内容经由算术逻辑单元被添加到第二寄存器的内容。第二，对于当前部分中的“1”的每个其他位，移位和加法运算是通过预定机器将第一寄存器的内容移位等于位置数位位于当前部分的低位位置的左侧，并且经由算术逻辑单元将第一寄存器的预定内容相加到第二寄存器的内容。第三，对于不包含第一被乘数的低位的多个部分的每个部分，第一个寄存器“n”位的内容向左移位。

16. 发明授权

US4601018A Banked memory circuit 失效
标题翻译：存储器电路
公开(公告)号：US4601018A
公开(公告)日：1986-07-15
申请号：US696038
申请日：1985-01-29
申请人： Allen Baum , Peter Baum
发明人： Allen Baum , Peter Baum
IPC分类号： G06F12/06 , G06T1/60 , G11C8/12 , G11C11/406 , G11C11/30
CPC分类号： G06F12/0623 , G06T1/60 , G11C11/406 , G11C8/12
摘要： A memory circuit for interconnection to a computer including several memory banks, each bank including memory for the storage of information for the total address space addressable by the data processor. The memory circuit further includes a bank selection circuit connected to the data processor for receiving data representing a selected one of the memory banks. The memory circuit further includes a memory access circuit that determines from the bank selection circuit which one of the memory banks has been selected and provides alternating access between the selected memory bank and a specific memory bank in accordance with a timing signal from the data processor. The specific data bank includes display information and is accessed by the data processor during each interval when information is being output to the display. The memory circuit further includes a memory refresh circuit to refresh the memory banks by refreshing a limited number of memory banks during successive refresh time intervals in accordance with control signals from the display circuitry.
摘要翻译：一种用于与包括几个存储体的计算机互连的存储器电路，每个存储体包括用于存储由数据处理器寻址的总地址空间的信息的存储器。存储器电路还包括连接到数据处理器的存储体选择电路，用于接收表示所选存储体组中的一个的数据。存储器电路还包括存储器存取电路，其从存储体选择电路确定已经选择了哪个存储体，并且根据来自数据处理器的定时信号，提供所选存储体和特定存储体之间的交替存取。特定数据库包括显示信息，并且当信息被输出到显示器时在数据处理器在每个间隔期间被访问。存储器电路还包括存储器刷新电路，以根据来自显示电路的控制信号在连续的刷新时间间隔期间刷新有限数量的存储体来刷新存储体。

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