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11. 发明申请

US20150243598A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150243598A1
公开(公告)日：2015-08-27
申请号：US14423020
申请日：2012-09-17
申请人： Institute Of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L23/528 , H01L21/311 , H01L21/3213 , H01L23/532 , H01L21/768
CPC分类号： H01L23/528 , H01L21/31111 , H01L21/32133 , H01L21/76802 , H01L21/76831 , H01L21/76838 , H01L21/76841 , H01L21/76877 , H01L21/76892 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：a）在衬底上形成金属互连衬垫; b）形成掩模层以覆盖金属互连衬里并在掩模层上形成露出金属互连衬套的开口; c）经由开口蚀刻和断开金属互连衬套，由此绝缘和隔离金属互连衬套。本发明还提供一种半导体结构，其包括衬底和金属互连衬套，其中金属互连衬里的端部通过在衬底内形成的绝缘壁而断开。本发明提供的结构和方法有利于缩短相邻金属互连衬套的端部之间的距离，节省器件面积并抑制金属互连衬套发生的短路。

12. 发明授权

US11251184B2 Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权
公开(公告)号：US11251184B2
公开(公告)日：2022-02-15
申请号：US17039770
申请日：2020-09-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Yanbo Zhang , Huicai Zhong
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66 , H01L21/8234
摘要： A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

13. 发明授权

US10128351B2 Semiconductor devices having a gate conductor and methods of manufacturing the same 有权
公开(公告)号：US10128351B2
公开(公告)日：2018-11-13
申请号：US14389095
申请日：2012-10-08
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/49 , H01L21/28 , H01L27/11568 , H01L21/8238 , H01L29/423
摘要： Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

14. 发明授权

US10833086B2 Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权
公开(公告)号：US10833086B2
公开(公告)日：2020-11-10
申请号：US16461330
申请日：2016-12-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Yanbo Zhang , Huicai Zhong
IPC分类号： H01L27/092 , H01L21/033 , H01L21/3105 , H01L21/311 , H01L21/8238 , H01L27/02 , H01L29/08 , H01L29/66 , H01L29/78 , H01L21/28 , H01L29/423 , H01L21/027 , H01L29/10 , H01L29/36
摘要： A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

15. 发明申请

US20170288037A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170288037A1
公开(公告)日：2017-10-05
申请号：US15630356
申请日：2017-06-22
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/49 , H01L21/8234 , H01L29/78 , H01L27/02 , H01L29/66 , H01L21/768 , H01L27/088
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L27/1052 , H01L27/10888 , H01L27/10891 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.

16. 发明申请

US20150221768A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150221768A1
公开(公告)日：2015-08-06
申请号：US14423132
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao , Jun Luo
IPC分类号： H01L29/78 , H01L29/417 , H01L29/40 , H01L29/66
CPC分类号： H01L29/7845 , H01L29/0688 , H01L29/0847 , H01L29/165 , H01L29/401 , H01L29/4175 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a semiconductor structure is disclosed. The method comprises: providing a substrate, forming a gate stack on the substrate and forming source/drain regions within the substrate; etching the source/drain regions to form trenches; forming a contact layer on the surface of the source/drain regions that have been etched; forming a stress material layer within the trenches; depositing an interlayer dielectric layer and forming contact plugs in contact with the stress material. Accordingly, a semiconductor structure is also disclosed. In the present invention, trenches are formed by etching source/drain regions in order to increase exposed areas at the source/drain regions, a contact layer is formed on the surface of the source/drain regions, and a stress material is filled into the trenches, which is capable of reducing effectively contact resistance between the contact layer and source/drain regions while introducing stress into channels, and thereby enhancing carrier mobility and improving performance of semiconductor structures.
摘要翻译：公开了一种制造半导体结构的方法。该方法包括：提供衬底，在衬底上形成栅堆叠并在衬底内形成源/漏区; 蚀刻源/漏区以形成沟槽; 在已经被蚀刻的源极/漏极区域的表面上形成接触层; 在沟槽内形成应力材料层; 沉积层间电介质层并形成与应力材料接触的接触塞。因此，还公开了一种半导体结构。在本发明中，通过蚀刻源极/漏极区域形成沟槽，以便增加源极/漏极区域的暴露区域，在源极/漏极区域的表面上形成接触层，并且将应力材料填充到沟槽，其能够在将应力引入沟道中同时有效地降低接触层和源极/漏极区之间的接触电阻，从而增强载流子迁移率并提高半导体结构的性能。

17. 发明申请

US20150054073A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150054073A1
公开(公告)日：2015-02-26
申请号：US14389055
申请日：2012-11-26
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/2658 , H01L21/26586 , H01L29/105 , H01L29/1083 , H01L29/4983 , H01L29/6653 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7833 , H01L29/7835 , H01L29/7843
摘要： Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.
摘要翻译：提供半导体器件及其制造方法。在一个实施例中，该方法可以包括：在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并且以所述第二屏蔽层为掩模形成所述源极和漏极区域中的另一个; 去除所述源极和漏极区域中另一个旁边的所述第二屏蔽层的一部分; 形成栅极电介质层，并且在所述第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体; 以及在所述衬底上形成应力层状介电层。

18. 发明申请

US20140357027A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140357027A1
公开(公告)日：2014-12-04
申请号：US14364950
申请日：2012-03-23
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
IPC分类号： H01L21/8238 , H01L29/417 , H01L29/45 , H01L21/84
CPC分类号： H01L21/823814 , H01L21/2255 , H01L21/28518 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/41725 , H01L29/45 , H01L29/456 , H01L29/665
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.
摘要翻译：本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域。根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

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