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11. 发明授权

US09349484B2 Sample-and-hold circuit for an interleaved analog-to-digital converter 有权
标题翻译：用于交错模数转换器的采样和保持电路
公开(公告)号：US09349484B2
公开(公告)日：2016-05-24
申请号：US14808267
申请日：2015-07-24
申请人： IMEC VZW
发明人： Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
IPC分类号： H03M1/00 , G11C27/02 , H03M1/12
CPC分类号： G11C27/02 , H03M1/1245
摘要： The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
摘要翻译：本公开涉及一种采样和保持电路，包括：晶体管，被布置用于在采样模式和保持模式之间切换;以及自举电路，布置成用于在采样模式中保持源极端子和栅极端子之间的电压电平晶体管与源极端子处的电压无关，并且被设置为在保持模式下关断晶体管。引导电路包括自举电容，其布置成在保持模式期间被预充电到给定电压，自举电容在采样模式期间连接在源极端子和栅极端子之间。在一个示例中，自举电路包括用于产生给定电压的开关电容器电荷泵。

12. 发明授权

US11764799B2 Time-interleaved analog-to-digital converter and conversion method thereof 有权
公开(公告)号：US11764799B2
公开(公告)日：2023-09-19
申请号：US17569061
申请日：2022-01-05
申请人： IMEC VZW
发明人： Jan Craninckx , Ewout Martens
IPC分类号： H03M1/12 , H03M1/10 , H03M1/18 , H04N25/75 , H03M1/56 , H04N5/06
CPC分类号： H03M1/1215 , H03M1/1023 , H03M1/187 , H03M1/56 , H04N5/06 , H04N25/75 , H03M1/123
摘要： Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.

13. 发明申请

US20210399685A1 Odd Harmonic Generation Device and Method 有权
公开(公告)号：US20210399685A1
公开(公告)日：2021-12-23
申请号：US17328181
申请日：2021-05-24
申请人： IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
发明人： Sehoon Park , Jan Craninckx , Pierre Wambacq , Davide Guermandi
IPC分类号： H03B19/14 , H03K5/00
摘要： An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

14. 发明申请

US20210104976A1 Method of Calibrating and a Calibration Circuit for a Two-Point Modulation Phase Locked Loop 有权
公开(公告)号：US20210104976A1
公开(公告)日：2021-04-08
申请号：US17061147
申请日：2020-10-01
申请人： IMEC VZW
发明人： Nereo Markulic , Jan Craninckx , Miguel Glassee
IPC分类号： H03C3/09 , H03L7/099 , H03L7/093
摘要： The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.

15. 发明授权

US10516423B2 Polar transmitter and method for generating a transmit signal using a polar transmitter 有权
公开(公告)号：US10516423B2
公开(公告)日：2019-12-24
申请号：US15621214
申请日：2017-06-13
申请人： IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
发明人： Nereo Markulic , Jan Craninckx
IPC分类号： H03C3/09 , H03C5/00 , H04B1/04 , H04L7/00 , H04B17/11 , H04L27/36 , H04L7/033 , H04L27/04 , H04L27/152
摘要： A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.

16. 发明授权

US09832051B2 Front-end system for a radio device 有权
公开(公告)号：US09832051B2
公开(公告)日：2017-11-28
申请号：US15043768
申请日：2016-02-15
申请人： IMEC VZW , Vrije Universiteit Brussel
发明人： Jan Craninckx , Mark Ingels , Pedro Emiliano Paro Filho
IPC分类号： H04L27/00 , H04B1/04 , H04B1/18
CPC分类号： H04L27/0002 , H04B1/0475 , H04B1/0483 , H04B1/18 , H04B2001/0491
摘要： The present disclosure relates to a front-end system for a radio device comprising: a charge generator circuit arranged for receiving a digital baseband signal, a first converter circuit arranged for calculating at least one charge value based on the digital baseband signal, a second converter circuit arranged for converting the at least one charge value into at least one electrical charge, and a modulator circuit arranged for generating a radio frequency signal based on the at least one electrical charge and at least one local oscillator signal.

17. 发明授权

US09166608B1 Method and circuit for bandwidth mismatch estimation in an A/D converter 有权
标题翻译： A / D转换器带宽失配估计的方法和电路
公开(公告)号：US09166608B1
公开(公告)日：2015-10-20
申请号：US14731471
申请日：2015-06-05
申请人： IMEC VZW
发明人： Kazuaki Deguchi , Bob Verbruggen , Jan Craninckx
IPC分类号： H03M1/10 , H03M1/06 , H03M1/00 , H03M1/46 , H03M1/12
CPC分类号： H03M1/0604 , H03M1/00 , H03M1/002 , H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/1215 , H03M1/14 , H03M1/468 , H03M2201/4233
摘要： Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.
摘要翻译：这里的方法和装置涉及用于估计时间交织的A / D转换器中的带宽不匹配的方法。示例性方法包括：在多个通道的每个通道中将电容器的端子预充电到第一状态，并对通过第一可切换路径施加的参考模拟输入电压信号（Vref）进行采样，由此在第一端子处接收采样的输入电压信号电容器该方法还包括将每个信道的第二终端设置为第二状态。该方法还包括经由第二可切换路径将参考模拟输入电压信号施加到第一端子，从而在第一端子上产生非零稳定误差。该方法另外包括量化沉降误差以获得非零建立误差的估计。该方法还包括比较非零建立误差的估计并导出带宽不匹配的估计。

18. 发明公开

US20230299478A1 Phased Array Transceiver Element 审中-公开
公开(公告)号：US20230299478A1
公开(公告)日：2023-09-21
申请号：US18185181
申请日：2023-03-16
申请人： IMEC VZW
发明人： Yang Zhang , Jan Craninckx , Pierre Wambacq , Giuseppe Gramegna
IPC分类号： H01Q3/34 , H01P1/213 , H01P5/12 , H04B7/0408
CPC分类号： H01Q3/34 , H01P1/213 , H01P5/12 , H04B7/0408
摘要： A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator signal, and applying the secondary frequency multiplication factor.

19. 发明授权

US11476858B2 Advanced successive approximation register analog-to-digital converter and corresponding method 有权
公开(公告)号：US11476858B2
公开(公告)日：2022-10-18
申请号：US17221166
申请日：2021-04-02
申请人： Imec vzw
发明人： Ewout Martens , Davide Dermit , Jan Craninckx
IPC分类号： H03M1/06 , H03M1/10 , H03M1/46
摘要： An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

20. 发明申请

US20210181775A1 Device and Method for Enhancing Voltage Regulation Performance 有权
公开(公告)号：US20210181775A1
公开(公告)日：2021-06-17
申请号：US17123299
申请日：2020-12-16
申请人： IMEC VZW
发明人： Nereo Markulic , Benjamin Hershberg , Jorge Luis Lagos Benites , Ewout Martens , Jan Craninckx
IPC分类号： G05F1/565 , G05F1/46
摘要： A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

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