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11. 发明授权

US08531001B2 Complementary bipolar inverter 有权
标题翻译：互补双极型逆变器
公开(公告)号：US08531001B2
公开(公告)日：2013-09-10
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

12. 发明授权

US07417288B2 Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
标题翻译：用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
公开(公告)号：US07417288B2
公开(公告)日：2008-08-26
申请号：US11311462
申请日：2005-12-19
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L29/76
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

13. 发明授权

US08859302B2 Structure and method for adjusting threshold voltage of the array of transistors 有权
标题翻译：用于调整晶体管阵列的阈值电压的结构和方法
公开(公告)号：US08859302B2
公开(公告)日：2014-10-14
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L21/66 , G11C11/412 , H01L27/11 , H01L27/12 , H01L21/84 , H01L27/115 , H01L29/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译：一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

14. 发明授权

US08735990B2 Radiation hardened FinFET 有权
标题翻译：辐射硬化FinFET
公开(公告)号：US08735990B2
公开(公告)日：2014-05-27
申请号：US11679869
申请日：2007-02-28
申请人： Brent A. Anderson , Robert H. Dennard , Mark C. Hakey , Edward J. Nowak
发明人： Brent A. Anderson , Robert H. Dennard , Mark C. Hakey , Edward J. Nowak
IPC分类号： H01L21/70 , H01L27/085 , H01L29/06
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7851
摘要： The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.
摘要翻译：本发明的实施例提供了一种用于Rad-hard FinFET或台面的结构和方法。更具体地，提供了具有至少一个翅片或台面的半导体结构，其包括在隔离区域上的沟道区域。掺杂衬底区域也设置在鳍片的下方，其中掺杂衬底区域具有与沟道区域的第二极性相反的第一极性。隔离区域接触掺杂衬底区域。该结构还包括覆盖沟道区域和隔离区域的至少一部分的栅电极。栅极电极包括在鳍片的沟道区域下方的下部，其中栅电极的下部包括至少翅片厚度的二分之一的高度。

15. 发明授权

US08492838B2 Isolation structures for SOI devices with ultrathin SOI and ultrathin box 有权
标题翻译：具有超薄SOI和超薄盒的SOI器件的隔离结构
公开(公告)号：US08492838B2
公开(公告)日：2013-07-23
申请号：US12618871
申请日：2009-11-16
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

16. 发明授权

US08445946B2 Gated diode memory cells 有权
标题翻译：门控二极管存储单元
公开(公告)号：US08445946B2
公开(公告)日：2013-05-21
申请号：US10735061
申请日：2003-12-11
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： H01L27/108 , G11C11/36
CPC分类号： G11C11/405
摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
摘要翻译：提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

17. 发明授权

US08324667B2 Amplifiers using gated diodes 有权
公开(公告)号：US08324667B2
公开(公告)日：2012-12-04
申请号：US10751714
申请日：2004-01-05
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： H01L29/94
CPC分类号： H03F1/56 , G11C7/06 , H01L27/0811 , H01L29/7391 , H03F2200/183
摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

18. 发明申请

US20120302039A1 ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX 失效
标题翻译：具有超薄SOI和ULTRATHIN BOX的SOI器件的隔离结构
公开(公告)号：US20120302039A1
公开(公告)日：2012-11-29
申请号：US13566568
申请日：2012-08-03
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/762
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

19. 发明授权

US08276002B2 Power delivery in a heterogeneous 3-D stacked apparatus 有权
标题翻译：在异种3-D堆叠设备中的功率输送
公开(公告)号：US08276002B2
公开(公告)日：2012-09-25
申请号：US12623462
申请日：2009-11-23
申请人： Robert H. Dennard , Eren Kursun
发明人： Robert H. Dennard , Eren Kursun
IPC分类号： G06F1/00 , G06F1/26 , G06F17/50 , H01L23/02 , H01L23/52 , H02J1/10 , B23K11/24 , H02M7/00
CPC分类号： H01L25/18 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , Y10T307/50
摘要： A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
摘要翻译：提供了一种不均匀的三维（3-D）层叠装置，其包括以堆叠配置布置的多个层，其中下层被配置为接收板级电压，以及堆叠在下层上方的一个或多个上层。异质三维层叠装置还包括每层多个瓦片，其中每个瓦片被设计成接收单独调节的电压。异质三层堆叠装置还包括在一个或多个上层中的至少一个层，其中电压转换器提供从板级电压转换的单独调节的电压。

20. 发明申请

US20110115553A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 有权
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20110115553A1
公开(公告)日：2011-05-19
申请号：US12619285
申请日：2009-11-16
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F1/10 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

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