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11. 发明授权

US5313579A B-ISDN sequencer chip device 失效
标题翻译： B-ISDN音序器芯片设备
公开(公告)号：US5313579A
公开(公告)日：1994-05-17
申请号：US893266
申请日：1992-06-04
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5615 , H04L2012/5619 , H04L2012/5636 , H04L2012/5651 , H04L2012/5681
摘要： A sequencer chip device, provided for use in a broadband integrated service digital network (B-ISDN), is particularly adapted to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node surface interface (NNI) by a queue manager. The traffic enforcer contains a buffer to delay and reshape violating cells that do not comply with some agreed-upon traffic parameters. The queue manager manages cells in a queue at network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Proposed architectures for the traffic enforcer and the queue manager include the chip device. The chip device includes a plurality of modules each of which is divided into three main functional areas: controller, memory and comparator. The chip device is preferably implemented using 1.2 .mu.m CMOS technology.
摘要翻译：提供用于宽带综合业务数字网络（B-ISDN）的定序器芯片装置特别适用于在网络的两个地方控制用户的业务：在业务执行者的用户网络接口（UNI）并在队列管理器的网络节点表面接口（NNI）上。流量执行者包含一个缓冲区，用于延迟和重塑不符合某些商定的流量参数的违反细胞。队列管理器在网络节点处管理队列中的小区，使得始终首先提供较高优先级的小区，当队列满时，丢弃低优先级小区，并且防止相同优先级小区之间的任何干扰。流量执行者和队列管理器的建议架构包括芯片设备。芯片装置包括多个模块，每个模块分为三个主要功能区域：控制器，存储器和比较器。芯片器件优选使用1.2μmCMOS技术实现。

12. 发明授权

US5204882A Service clock recovery for variable bit rate services 失效
标题翻译：可变比特率服务的服务时钟恢复
公开(公告)号：US5204882A
公开(公告)日：1993-04-20
申请号：US846769
申请日：1992-03-06
申请人： Hung-Hsiang J. Chao , Cesar A. Johnston
发明人： Hung-Hsiang J. Chao , Cesar A. Johnston
IPC分类号： H04J3/06 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04J3/0632 , H04L2012/5616 , H04L2012/5672
摘要： To recover the service clock of a variable bit rate source (170) which generates data at a rate which is not proportional to a service clock (76), timing cells are generated. The timing cells are generated at a rate which is proportional to the service clock (76). The timing cells and data are transmitted via a network (100). At the receive-end, the data is stored in a buffer (82). A phase locked loop (90') generates a local clock signal in the form of a read signal which controls the rate at which the received data is read out of the buffer (82). The read signal produced by the phase locked loop (90') is proportional to the average rate at which timing cells are received at the receive-end. In this manner the signal which reads the data out of the buffer (82) at the receive-end approaches the service clock (76) at the source end.
摘要翻译：为了恢复以与服务时钟（76）不成比例的速率生成数据的可变比特率源（170）的服务时钟，产生定时单元。定时单元以与服务时钟（76）成比例的速率产生。定时单元和数据经由网络（100）发送。在接收端，数据存储在缓冲器（82）中。锁相环（90'）以读取信号的形式产生本地时钟信号，该读信号控制从缓冲器（82）读出接收数据的速率。由锁相环（90'）产生的读信号与在接收端接收定时单元的平均速率成比例。以这种方式，在接收端读取缓冲器（82）中的数据的信号在源端接近服务时钟（76）。

13. 发明授权

US5007070A Service clock recovery circuit 失效
标题翻译：服务时钟恢复电路
公开(公告)号：US5007070A
公开(公告)日：1991-04-09
申请号：US429840
申请日：1989-10-31
申请人： Hung-Hsiang J. Chao , Cesar A. Johnston
发明人： Hung-Hsiang J. Chao , Cesar A. Johnston
IPC分类号： H04J3/06
CPC分类号： H04J3/0632
摘要： A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.
摘要翻译：时钟恢复电路用于从不在预定时间到达并且可能是突发的数据恢复时钟信号。时钟恢复电路与接收数据的缓冲器一起工作。说明性地，时钟恢复电路维持写入缓冲器的数据的字节的第一计数，以及从缓冲器传送的数据的字节的第二计数。减法器从第一计数器减去第二计数，并且判定电路利用结果来提供指示缓冲器的当前占用的信号。根据当前占用率，时钟恢复电路的输出信号的频率增加，减小或维持为恒定。因此，该输出信号用作恢复的时钟信号。

14. 发明授权

US4855999A DTDM multiplexer with cross-point switch 失效
标题翻译：具有交叉点开关的DTDM多路复用器
公开(公告)号：US4855999A
公开(公告)日：1989-08-08
申请号：US118979
申请日：1987-11-10
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04J3/16 , H04J3/24 , H04L12/64
CPC分类号： H04L12/64 , H04J3/1682 , H04J3/247
摘要： A multiplexer for combining a plurality of relatively sparsely occupied DTDM bit streams into a smaller number of more densely occupied DTDM bit streams at the same bit rate is disclosed. The input lines of the multiplexer are divided into groups so that DTDM frames arriving on the input lines in one group are combined to form one outgoing DTDM bit stream. The outgoing DTDM bit streams are formed by synchronously generating chain of empty frames for each of the input line groups. The frames in a chain are passed to a first member of the appropriate input line group and by means of a cross-point switch to each succeeding member for the insertion of data. The groupings of input lines are defined by the settings of the cross-point switch and may be rearranged by changing the settings of the switch.
摘要翻译：公开了一种多路复用器，用于将多个相对稀疏占用的DTDM比特流以相同比特率组合成较少数量的更密集占用的DTDM比特流。复用器的输入线被分成组，使得到达一组中的输入线的DTDM帧被组合以形成一个输出的DTDM比特流。输出的DTDM比特流通过为每个输入线路组同步产生空帧链来形成。链中的帧被传递到适当输入线组的第一成员，并且通过交叉点切换传递给每个后续成员用于插入数据。输入线的分组由交叉点开关的设置定义，可以通过更改开关的设置进行重新排列。

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