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11. 发明申请

US20080256345A1 Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System 失效
标题翻译：当处理器在信息处理系统中遇到低置信度时通过调节指令获取来节省电力的方法和装置
公开(公告)号：US20080256345A1
公开(公告)日：2008-10-16
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

12. 发明授权

US07380104B2 Method and apparatus for back to back issue of dependent instructions in an out of order issue queue 失效
标题翻译：方法和装置，用于在乱序问题队列中反向发布依赖指令
公开(公告)号：US07380104B2
公开(公告)日：2008-05-27
申请号：US11380078
申请日：2006-04-25
申请人： William Elton Burky , Raymond Cheung Yeung
发明人： William Elton Burky , Raymond Cheung Yeung
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/3836 , G06F9/3838
摘要： A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.
摘要翻译：提供了一种用于在队列的特定周期期间评估出故障发送队列中的两个或更多个指令的方法，以在下一个后续周期中选择要发出的指令。如果先前指定在特定周期内发出指令，则会对队列中的一个或多个指令进行评估，以确定其中任何一个是否依赖于指定的指令。对于评估，放置到队列中的每条指令都伴随有相应的逻辑元素，为指令提供目标到源的比较。在包括方法的实施例中，识别在特定周期期间队列中最早的就绪指令。当先前指定在特定周期期间发出指令时，确定队列中的至少第一指令是否符合一组条件中的每个条件，该集合至少包括第一指令依赖于的条件指定的指令，并且第一条指令比最早的就绪指令更旧。仅当第一条指令符合该组中的每个条件时，才在下一个后续周期中选择第一条指令进行发布。

13. 发明授权

US08255669B2 Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence information 有权
标题翻译：基于包括分支置信度的分支问题信息在多线程处理器中进行线程优先级控制的方法和装置
公开(公告)号：US08255669B2
公开(公告)日：2012-08-28
申请号：US12023004
申请日：2008-01-30
申请人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
发明人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
IPC分类号： G06F9/32
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/3844 , G06F9/3861
摘要： An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.
摘要翻译：信息处理系统采用包括线程优先级控制器的处理器。当指令线程的分支指令发生时，处理器中的问题单元向线程优先级控制器发送分支发出信息。在一个实施例中，如果分支发布信息在分支指令的分支预测中表示低置信度，则线程优先级控制器推测地增加或提高包含该低置信度分支指令的指令线程的优先级。以这种方式，如果分支重定向实际上由于错误的预测而发生，则提取器准备好比存储器阵列更快地访问存储器阵列中的重定向地址。

14. 发明授权

US07925853B2 Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system 有权
标题翻译：当处理器在信息处理系统中执行低置信度分支指令时，用于控制存储器阵列门控的方法和装置
公开(公告)号：US07925853B2
公开(公告)日：2011-04-12
申请号：US11969344
申请日：2008-01-04
申请人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
发明人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F1/3203 , G06F1/3237 , G06F1/3275 , G06F9/3804 , G06F9/3844 , G06F2212/6028 , Y02D10/128 , Y02D10/13 , Y02D10/14
摘要： An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely.
摘要翻译：信息处理系统包括具有阵列功率管理控制器的处理器。阵列功率管理控制器关闭诸如高速缓存之类的存储器阵列，以便当分组指令队列中的一组指令作为一组显示出对其中的分支指令的分支预测的准确性的置信度时，节省功率，其小于第一预定阈值置信阈值。在信息处理系统的一个实施例中，当对特定当前发出的分支指令的分支预测的精度的置信度表现出小于第二预定阈值置信阈值时，阵列功率管理控制器推测性地禁止存储器阵列的选通。以这种方式，阵列功率管理控制器再次允许在分支重定向可能的情况下访问存储器阵列。

15. 发明授权

US07669038B2 Method and apparatus for back to back issue of dependent instructions in an out of order issue queue 失效
标题翻译：方法和装置，用于在乱序问题队列中反向发布依赖指令
公开(公告)号：US07669038B2
公开(公告)日：2010-02-23
申请号：US12114010
申请日：2008-05-02
申请人： William Elton Burky , Raymond Cheung Yeung
发明人： William Elton Burky , Raymond Cheung Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838
摘要： A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.
摘要翻译：提供了一种用于在队列的特定周期期间评估出故障发送队列中的两个或更多个指令的方法，以在下一个后续周期中选择要发出的指令。如果先前指定在特定周期内发出指令，则会对队列中的一个或多个指令进行评估，以确定其中任何一个是否依赖于指定的指令。对于评估，放置到队列中的每条指令都伴随有相应的逻辑元素，为指令提供目标到源的比较。在包括方法的实施例中，识别在特定周期期间队列中最早的就绪指令。当先前指定在特定周期期间发出指令时，确定队列中的至少第一指令是否符合一组条件中的每个条件，该集合至少包括第一指令依赖于的条件指定的指令，并且第一条指令比最早的就绪指令更旧。仅当第一条指令符合该组中的每个条件时，才在下一个后续周期中选择第一条指令进行发布。

16. 发明申请

US20090193231A1 METHOD AND APPARATUS FOR THREAD PRIORITY CONTROL IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM 有权
标题翻译：信息处理系统的多线程处理器中的线程优先级控制方法与装置
公开(公告)号：US20090193231A1
公开(公告)日：2009-07-30
申请号：US12023004
申请日：2008-01-30
申请人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
发明人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/3844 , G06F9/3861
摘要： An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.
摘要翻译：信息处理系统采用包括线程优先级控制器的处理器。当指令线程的分支指令发生时，处理器中的问题单元向线程优先级控制器发送分支发出信息。在一个实施例中，如果分支发布信息在分支指令的分支预测中表示低置信度，则线程优先级控制器推测地增加或提高包含该低置信度分支指令的指令线程的优先级。以这种方式，如果分支重定向实际上由于错误的预测而发生，则提取器准备好比存储器阵列更快地访问存储器阵列中的重定向地址。

17. 发明申请

US20090177858A1 Method and Apparatus for Controlling Memory Array Gating when a Processor Executes a Low Confidence Branch Instruction in an Information Handling System 有权
标题翻译：用于在处理器执行信息处理系统中的低置信度分支指令时控制存储器阵列门控的方法和装置
公开(公告)号：US20090177858A1
公开(公告)日：2009-07-09
申请号：US11969344
申请日：2008-01-04
申请人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
发明人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F1/3203 , G06F1/3237 , G06F1/3275 , G06F9/3804 , G06F9/3844 , G06F2212/6028 , Y02D10/128 , Y02D10/13 , Y02D10/14
摘要： An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely.
摘要翻译：信息处理系统包括具有阵列功率管理控制器的处理器。阵列功率管理控制器关闭诸如高速缓存之类的存储器阵列，以便当分组指令队列中的一组指令作为一组显示出对其中的分支指令的分支预测的准确性的置信度时，节省功率，其小于第一预定阈值置信阈值。在信息处理系统的一个实施例中，当对特定当前发出的分支指令的分支预测的精度的置信度表现出小于第二预定阈值置信阈值时，阵列功率管理控制器推测性地禁止存储器阵列的选通。以这种方式，阵列功率管理控制器再次允许在分支重定向可能的情况下访问存储器阵列。

18. 发明申请

US20090150657A1 Method and Apparatus for Inhibiting Fetch Throttling When a Processor Encounters a Low Confidence Branch Instruction in an Information Handling System 有权
标题翻译：当处理器在信息处理系统中遇到低置信分支指令时，用于抑制提取节流的方法和装置
公开(公告)号：US20090150657A1
公开(公告)日：2009-06-11
申请号：US11951112
申请日：2007-12-05
申请人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
发明人： Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3802 , G06F9/3804
摘要： An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.
摘要翻译：信息处理系统包括处理器，其每当分支指令队列中的一组指令一起表现出对小于第一预定阈值置信阈值的分支指令的分支预测的精度的置信度时，可以节制指令获取器。在一个实施例中，处理器包括取消节流控制器，当对当前发出的特定分支指令的分支预测的准确度的置信度小于第二预定阈值置信阈值时，该指令节省控制器禁止指令获取器的获取节流。

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