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11. 发明授权

US07388257B2 Multi-gate device with high k dielectric for channel top surface 有权
标题翻译：具有高k电介质的多栅极器件用于沟道顶表面
公开(公告)号：US07388257B2
公开(公告)日：2008-06-17
申请号：US10711200
申请日：2004-09-01
申请人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

12. 发明申请

US20060043421A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 有权
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20060043421A1
公开(公告)日：2006-03-02
申请号：US10711200
申请日：2004-09-01
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

13. 发明申请

US20080070366A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 失效
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20080070366A1
公开(公告)日：2008-03-20
申请号：US11928787
申请日：2007-10-30
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

14. 发明授权

US07749842B2 Structures and methods for making strained MOSFETs 有权
标题翻译：制造应变MOSFET的结构和方法
公开(公告)号：US07749842B2
公开(公告)日：2010-07-06
申请号：US11754627
申请日：2007-05-29
申请人： Huilong Zhu , Steven W. Bedell , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Steven W. Bedell , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block. Accordingly, a semiconductor device having a strained Si fin vertically oriented on a non-conductive substrate may be formed where the strained Si film is oriented such that it may form a channel of small dimensions allowing access to both sides and top in order to from single gate, double gate, or more gate MOSFETs and finFETs with a channel having a reduced number of defects and/or reduced dimensions.
摘要翻译：提供了提供具有减小的缺陷的应变Si膜的方法和装置，其中应变Si膜在非导电基板的表面上形成垂直取向的翅片。应变Si膜或翅片可以形成具有相对较小尺寸的半导体通道，同时也具有很少的缺陷。应变Si翅片通过在松弛的SiGe块的一侧生长Si而形成。可以在应变Si膜的表面上形成诸如氧化物，高“k”材料或两者的组合的电介质栅极。另外，在基本上不影响应变Si膜中的应力的情况下，可以去除弛豫的SiGe块，以允许在松弛的SiGe块先前占据的表面上形成第二栅极氧化物。因此，可以形成具有垂直取向在非导电衬底上的应变Si鳍片的半导体器件，其中应变Si膜被定向成使得其可以形成允许接近两侧和顶部的小尺寸的通道，以便从单个栅极，双栅极或更多栅极MOSFET和finFET，沟道具有减少的缺陷数量和/或减小的尺寸。

15. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

16. 发明授权

US07091566B2 Dual gate FinFet 有权
标题翻译：双门FinFet
公开(公告)号：US07091566B2
公开(公告)日：2006-08-15
申请号：US10717737
申请日：2003-11-20
申请人： Huilong Zhu , Jochen Beintner , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Jochen Beintner , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7856
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。可以通过调整背偏置栅极电压来调整器件阈值。

17. 发明授权

US06939751B2 Method and manufacture of thin silicon on insulator (SOI) with recessed channel 失效
标题翻译：具有凹陷通道的薄绝缘体硅（SOI）的方法和制造
公开(公告)号：US06939751B2
公开(公告)日：2005-09-06
申请号：US10605726
申请日：2003-10-22
申请人： Huilong Zhu , Bruce B. Doris , Werner A. Rausch , Ying Zhang
发明人： Huilong Zhu , Bruce B. Doris , Werner A. Rausch , Ying Zhang
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66621 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/7842 , H01L29/78687
摘要： An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.
摘要翻译：具有凹陷沟道的RSD FET器件通过以下步骤形成有凸起的硅源和漏极以及形成在SOI结构（形成在衬底上的Si层）上的栅电极结构。在Si层上形成SiGe层，在SiGe上形成RSD层。通过RSD层和SiGe蚀刻以形成向下延伸到Si层的栅电极空间。形成一对被栅电极间隔开的RSD区域。用内部蚀刻停止层和内侧壁间隔物来排列栅电极空间的壁。在Si层上的内侧墙壁内部形成栅电极。在靠近内侧壁间隔物的RSD区域之间形成与栅电极相邻的外侧壁间隔物，并且掺杂RSD区域，由此在SOI硅层之间形成凹陷沟道，在SOI硅层之间的上升源极/漏极区域之间并且低于 SiGe层。

18. 发明授权

US07732874B2 FinFET structure using differing gate dielectric materials and gate electrode materials 有权
标题翻译： FinFET结构使用不同的栅介质材料和栅电极材料
公开(公告)号：US07732874B2
公开(公告)日：2010-06-08
申请号：US11847573
申请日：2007-08-30
申请人： Huilong Zhu , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/423
CPC分类号： H01L27/1211 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L29/785
摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.
摘要翻译：半导体结构包括第一finFET和第二finFET。第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

19. 发明申请

US20090057765A1 FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS 有权
标题翻译： FINFET结构使用不同的门电介质材料和门电极材料
公开(公告)号：US20090057765A1
公开(公告)日：2009-03-05
申请号：US11847573
申请日：2007-08-30
申请人： Huilong Zhu , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L29/785
摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.
摘要翻译：半导体结构包括第一finFET和第二finFET。第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

20. 发明授权

US06914303B2 Ultra thin channel MOSFET 有权
公开(公告)号：US06914303B2
公开(公告)日：2005-07-05
申请号：US10650229
申请日：2003-08-28
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

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