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11. 发明授权

US07569892B2 Method and structure for forming self-aligned, dual stress liner for CMOS devices 有权
标题翻译：用于形成CMOS器件自对准双应力衬垫的方法和结构
公开(公告)号：US07569892B2
公开(公告)日：2009-08-04
申请号：US11776584
申请日：2007-07-12
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

12. 发明授权

US07485510B2 Field effect device including inverted V shaped channel region and method for fabrication thereof 有权
标题翻译：包括倒V形沟道区域的场效应器件及其制造方法
公开(公告)号：US07485510B2
公开(公告)日：2009-02-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

13. 发明申请

US20080142852A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS 审中-公开
标题翻译：具有不同表面方向的主动区域的半导体器件结构
公开(公告)号：US20080142852A1
公开(公告)日：2008-06-19
申请号：US12032913
申请日：2008-02-18
申请人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

14. 发明申请

US20080057667A1 TEST STRUCTURE AND METHOD FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：通过短路分离区域接触短路检测的测试结构和方法
公开(公告)号：US20080057667A1
公开(公告)日：2008-03-06
申请号：US11469940
申请日：2006-09-05
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L21/76
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

15. 发明申请

US20080012019A1 METHOD AND STRUCTURE FOR FORMING SELF-ALIGNED, DUAL STRESS LINER FOR CMOS DEVICES 有权
标题翻译：用于形成用于CMOS器件的自对准双重应力衬垫的方法和结构
公开(公告)号：US20080012019A1
公开(公告)日：2008-01-17
申请号：US11776584
申请日：2007-07-12
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L27/108 , H01L21/31
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

16. 发明授权

US08138497B2 Test structure for detecting via contact shorting in shallow trench isolation regions 有权
标题翻译：用于检测浅沟槽隔离区域中接触短路的测试结构
公开(公告)号：US08138497B2
公开(公告)日：2012-03-20
申请号：US12140479
申请日：2008-06-17
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L23/544
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

17. 发明申请

US20080246032A1 TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：用于通过SHOREOW TRENCH隔离区域中的接触短路检测的测试结构
公开(公告)号：US20080246032A1
公开(公告)日：2008-10-09
申请号：US12140479
申请日：2008-06-17
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L21/66
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

18. 发明授权

US07416986B2 Test structure and method for detecting via contact shorting in shallow trench isolation regions 有权
标题翻译：在浅沟槽隔离区域通过接触短路检测的测试结构和方法
公开(公告)号：US07416986B2
公开(公告)日：2008-08-26
申请号：US11469940
申请日：2006-09-05
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L21/311
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

19. 发明申请

US20060068555A1 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US20060068555A1
公开(公告)日：2006-03-30
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

20. 发明授权

US06881635B1 Strained silicon NMOS devices with embedded source/drain 失效
标题翻译：具有嵌入式源极/漏极的应变硅NMOS器件
公开(公告)号：US06881635B1
公开(公告)日：2005-04-19
申请号：US10708746
申请日：2004-03-23
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
IPC分类号： C30B25/18 , C30B29/06 , H01L21/20 , H01L21/285 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/786 , C30B23/00 , H01L21/36
CPC分类号： H01L29/78696 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/28562 , H01L29/1054 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7834 , H01L29/78687
摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.
摘要翻译：由SiGe层支撑的应变硅层上的平面NFET通过在晶体管本体外部并且在应变硅层下方除去SiGe材料并且利用外延硅替代去除的材料来实现降低的外部电阻，从而为晶体管电极提供较低电阻并允许更好地控制砷的扩散。

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