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11. 发明授权

US07903046B2 Signal transmitter and a driving method thereof 有权
标题翻译：信号发射机及其驱动方法
公开(公告)号：US07903046B2
公开(公告)日：2011-03-08
申请号：US10907705
申请日：2005-04-12
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： G09G5/00
CPC分类号： G06F1/3209 , G06F1/3215 , G06F1/3218
摘要： A transmitter includes an output module coupled to an output port for outputting an output signal to the output port according to a detection signal, and a detect module for detecting the output port to generate the detect signal.
摘要翻译：发射机包括耦合到输出端口的输出模块，用于根据检测信号将输出信号输出到输出端口;以及检测模块，用于检测输出端口以产生检测信号。

12. 发明申请

US20090227222A1 WIRELESS RECEIVER WITH AUTOMATIC GAIN CONTROL AND METHOD FOR AUTOMATIC GAIN CONTROL OF RECEIVING CIRCUIT UTILIZED IN WIRELESS RECEIVER 有权
标题翻译：具有自动增益控制的无线接收机和无线接收机使用的接收电路自动增益控制方法
公开(公告)号：US20090227222A1
公开(公告)日：2009-09-10
申请号：US12041664
申请日：2008-03-04
申请人： Chao-Hsin Lu , Chang-Fu Kuo
发明人： Chao-Hsin Lu , Chang-Fu Kuo
IPC分类号： H04B1/06
CPC分类号： G01S19/23 , H03G3/3052
摘要： A wireless receiver with automatic gain control and a method for automatic gain control of a receiving circuit utilized in a wireless receiver are provided. The receiving circuit includes a programmable gain amplifier and a low noise amplifier, and the method includes: comparing a gain code of the programmable gain amplifier with a predetermined code range, wherein the gain code is determined by a frequency signal received through the low noise amplifier; and adjusting a gain of the low noise amplifier when the gain code is out of the predetermined code range.
摘要翻译：提供一种具有自动增益控制的无线接收机和用于无线接收机中的接收电路的自动增益控制方法。接收电路包括可编程增益放大器和低噪声放大器，该方法包括：将可编程增益放大器的增益代码与预定代码范围进行比较，其中增益代码由通过低噪声放大器接收的频率信号确定 ; 以及当所述增益代码超出所述预定代码范围时调整所述低噪声放大器的增益。

13. 发明授权

US07250793B2 Low voltage differential signaling driving apparatus 有权
标题翻译：低压差分信号驱动装置
公开(公告)号：US07250793B2
公开(公告)日：2007-07-31
申请号：US10754726
申请日：2004-01-12
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： H03B1/00
CPC分类号： H04L25/028
摘要： A low voltage differential signaling (LVDS) driving apparatus is disclosed, which comprises an LVDS output circuit to output an LVDS differential signal; a switch circuit coupled to the LVDS output circuit to control the phase of the LVDS differential signal; and a reference current control circuit to provide a control voltage to the LVDS output circuit such that the magnitude of the LVDS differential signal is determined based on the control voltage.
摘要翻译：公开了一种低压差分信号（LVDS）驱动装置，其包括用于输出LVDS差分信号的LVDS输出电路; 耦合到LVDS输出电路以控制LVDS差分信号的相位的开关电路; 以及参考电流控制电路，以向LVDS输出电路提供控制电压，使得基于控制电压确定LVDS差分信号的幅度。

14. 发明授权

US07242735B2 Data recovery system and the method thereof 有权
标题翻译：数据恢复系统及其方法
公开(公告)号：US07242735B2
公开(公告)日：2007-07-10
申请号：US10632925
申请日：2003-08-04
申请人： Chao-Hsin Lu , Yi-Shu Chang , Shiu-Rong Tong , Kuang-Hsi Hsieh
发明人： Chao-Hsin Lu , Yi-Shu Chang , Shiu-Rong Tong , Kuang-Hsi Hsieh
IPC分类号： H04L7/02
CPC分类号： H04L7/0338
摘要： A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.
摘要翻译：公开了一种数据恢复系统和方法，其包括过采样器，相位检测电路，数据拾取电路，数据重叠/跳过检测电路和数据校正电路。过采样器过采样输入信号，从而产生过采样信号。相位检测电路接收用于检测过采样信号的转变并输出相位信号。数据采集电路接收相位信号，相应地将过采样信号分组为n组，并选择一组作为输出数据。数据重叠/跳跃检测电路根据相位信号和最后的相位信号确定数据是否重叠或跳过。当数据重叠或跳过时，数据校正电路校正数据，并输出准确的输出数据。

15. 发明申请

US20060033543A1 Latch inverter and flip-flop using the same 有权
标题翻译：锁存逆变器和触发器使用相同
公开(公告)号：US20060033543A1
公开(公告)日：2006-02-16
申请号：US11200209
申请日：2005-08-10
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： H03K3/037
CPC分类号： H03K19/00323
摘要： A latch inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first level-adjusting unit and a second level-adjusting unit. The first level-adjusting unit changes the voltage level of the source of the second PMOS transistor in advance, and the second level-adjusting unit changes the voltage level of the drain of the second NMOS transistor in advance.
摘要翻译：锁存逆变器包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第一电平调整单元和第二电平调节单元。第一电平调整单元预先改变第二PMOS晶体管的源极的电压电平，并且第二电平调整单元预先改变第二NMOS晶体管的漏极的电压电平。

16. 发明申请

US20050083144A1 Adjustable voltage control oscillator 审中-公开
标题翻译：可调压控振荡器
公开(公告)号：US20050083144A1
公开(公告)日：2005-04-21
申请号：US10963160
申请日：2004-10-12
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： H03K3/03 , H03B1/00
CPC分类号： H03K3/0322
摘要： A voltage control oscillator (VCO) whose gain coefficient is adjustable outputs a clock signal according to a control voltage. The VCO includes a replica bias unit, at least a delay cell, coupled to the replica bias unit, and a loading circuit. The replica bias unit outputs a first operational voltage according to the control voltage. The delay cell includes a voltage control delay line for outputting an output differential signal according to an input differential signal. The frequency of the output differential signal is adjusted by changing the impedance of the loading circuit.
摘要翻译：增益系数可调的压控振荡器（VCO）根据控制电压输出时钟信号。 VCO包括复制偏压单元，耦合到复制偏压单元的至少延迟单元和加载电路。复制偏置单元根据控制电压输出第一工作电压。延迟单元包括用于根据输入差分信号输出输出差分信号的电压控制延迟线。通过改变负载电路的阻抗来调节输出差分信号的频率。

17. 发明申请

US20110029720A1 Flash Storage Device and Operation Method Thereof 有权
标题翻译：闪存存储设备及其操作方法
公开(公告)号：US20110029720A1
公开(公告)日：2011-02-03
申请号：US12641612
申请日：2009-12-18
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202
摘要： The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table.
摘要翻译：本发明提供一种闪存存储装置。在一个实施例中，闪存存储设备包括闪存和控制器。闪速存储器包括多个块，其中多个块中的每个块包括用于存储数据的多个页面，并且多个页面中的每一个具有物理地址。控制器将多个逻辑地址划分为多个逻辑地址范围，记录分别存储对应的逻辑地址范围的逻辑地址与对应的物理地址之间的映射关系的多个部分链接表，将部分链接表存储在闪存中存储器，组合部分链接表以获得链接表，并根据链接表将主机发送的逻辑地址转换为物理地址。

18. 发明授权

US07778321B2 Method for adjusting parameters of equalizer 有权
标题翻译：调整均衡器参数的方法
公开(公告)号：US07778321B2
公开(公告)日：2010-08-17
申请号：US11165029
申请日：2005-06-24
申请人： Yu-Pin Chou , Chao-Hsin Lu
发明人： Yu-Pin Chou , Chao-Hsin Lu
IPC分类号： H03K5/159
CPC分类号： H04L25/03019 , H04L2025/03764
摘要： A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.
摘要翻译：用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。首先，检测发送信号中的第一频带和第二频带的信号强度。然后比较第一频带和第二频带的信号强度以获得补偿比，即第一频带的总补偿量到第二频带。最后，根据补偿比的反馈调整均衡器的参数设置。因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

19. 发明申请

US20090190035A1 CIRCUIT FOR PROCESSING VIDEO SIGNAL 审中-公开
标题翻译：加工视频信号电路
公开(公告)号：US20090190035A1
公开(公告)日：2009-07-30
申请号：US12021310
申请日：2008-01-29
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： H03M1/12 , H04N5/14
CPC分类号： H04N5/16 , H04N5/14
摘要： Disclosed is a video signal processing circuit, which comprises: first and second DC level adjusting circuits, for adjusting the DC level of a video signal to generate a first adjusted video signal and a second adjusted video signal respectively; an analog to digital converter, for sampling a data signal of the video signal according to a target clock signal; a sync signal separating circuit, for separating a sync signal from the first adjusted video signal; a sync signal processor, for detecting the existence of the sync signal, and outputting a sync clock signal if the sync signal exists; a multiplexer, for outputting one of the sync clock signal or predetermined clock signal as the target clock signal according to a selecting signal; and a processor unit, for controlling the first DC level adjusting circuit, the second DC level adjusting circuit, and for generating the selecting signal.
摘要翻译：公开了一种视频信号处理电路，其包括：第一和第二DC电平调整电路，用于分别调整视频信号的直流电平以产生第一调整视频信号和第二调整视频信号; 模拟数字转换器，用于根据目标时钟信号对视频信号的数据信号进行采样; 同步信号分离电路，用于从第一调整视频信号中分离同步信号; 同步信号处理器，用于检测同步信号的存在;如果同步信号存在，则输出同步时钟信号; 多路复用器，用于根据选择信号输出同步时钟信号或预定时钟信号中的一个作为目标时钟信号; 以及处理器单元，用于控制第一DC电平调整电路，第二DC电平调整电路，并用于产生选择信号。

20. 发明申请

US20060078079A1 Clock generator and data recovery circuit using the same 有权
标题翻译：时钟发生器和数据恢复电路使用相同
公开(公告)号：US20060078079A1
公开(公告)日：2006-04-13
申请号：US11246090
申请日：2005-10-11
申请人： Chao-Hsin Lu
发明人： Chao-Hsin Lu
IPC分类号： H03D3/24
CPC分类号： H03L7/0996 , H03L7/087 , H03L7/0891 , H03L7/18 , H04L7/0338
摘要： A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal, a phase-frequency detector for receiving the selected clock and a reference clock and generating a phase-frequency error signal, a charge pump and loop filter for receiving the phase-frequency error signal and generating a control voltage, a phase detector for receiving the sampling clock and an input signal and generating a phase error signal, and a digital low-pass filter for receiving the phase error signal and generating the selection signal. The digital low-pass filter clears an accumulated phase error when it generates the selection signal to force the multiplexer to change the phase.
摘要翻译：时钟发生器和数据恢复电路。时钟发生器包括用于产生采样时钟和多相时钟的压控振荡器（VCO），多路复用器，用于接收多相时钟并根据选择信号选择多相时钟之一以产生所选择的时钟用于接收所选择的时钟和参考时钟并产生相位频率误差信号的相位频率检测器，用于接收相位频率误差信号并产生控制电压的电荷泵和环路滤波器，相位检测器，用于接收采样时钟和输入信号并产生相位误差信号，以及数字低通滤波器，用于接收相位误差信号并产生选择信号。当数字低通滤波器产生选择信号以使多路复用器改变相位时，会清除累积的相位误差。

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