专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07833890B2 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US07833890B2
公开(公告)日：2010-11-16
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

12. 发明授权

US07729164B2 Non-volatile memory device, method of operating the same, and method of fabricating the same 有权
标题翻译：非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US07729164B2
公开(公告)日：2010-06-01
申请号：US12010943
申请日：2008-01-31
申请人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
发明人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.
摘要翻译：非易失性存储器件可以包括至少一个半导体层，多个控制栅电极，多个电荷存储层，至少一个第一辅助电极和/或至少一个第二辅助电极。多个控制栅电极可以凹入半导体层。多个电荷存储层可以在多个控制栅电极和半导体层之间。第一和第二辅助电极可以被布置成彼此面对。多个控制栅电极可以在第一和第二辅助电极之间并与半导体层电容耦合。

13. 发明申请

US20100027316A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100027316A1
公开(公告)日：2010-02-04
申请号：US12465125
申请日：2009-05-13
申请人： TAE-EUNG YOON , Won-joo Kim , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： TAE-EUNG YOON , Won-joo Kim , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/025
摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.
摘要翻译：具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。提供耦合在多个位线和多个可变电阻器之间的多个选择晶体管。

14. 发明申请

US20090285027A1 Non-volatile memory devices and methods of operating non-volatile memory devices 有权
标题翻译：非易失性存储器件和操作非易失性存储器件的方法
公开(公告)号：US20090285027A1
公开(公告)日：2009-11-19
申请号：US12318651
申请日：2009-01-05
申请人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.
摘要翻译：提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。从多个位线确定用于编程的选择位线和用于防止编程的未选位线。对从多个字线中选择的至少一个禁止字线施加抑制电压。至少一个禁止字线包括最靠近字符串选择线定位的字线。将编程电压施加到从多个字线中选择的选定字线。数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

15. 发明申请

US20090253255A1 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US20090253255A1
公开(公告)日：2009-10-08
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

16. 发明授权

US07551491B2 Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof 有权
标题翻译：非易失性存储器件的单元，非易失性存储器件及其方法
公开(公告)号：US07551491B2
公开(公告)日：2009-06-23
申请号：US11715404
申请日：2007-03-08
申请人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
发明人： Won-joo Kim , Suk-pil Kim , Jae-woong Hyun , Yoon-dong Park , June-mo Koo
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.
摘要翻译：提供非易失性存储器件的单元电池及其方法。在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点，配置为执行并发存储器操作的第一和第二存储节点。在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底，分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成的第一遍栅极电极在第一位线区域和第一存储节点层之间的半导体衬底上，形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极，形成在半导体衬底上的第三栅极电极在所述第一和第二存储节点层之间形成第三位线区域，所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中，以及跨越所述第一和第二存储节点层延伸的控制栅电极。示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

17. 发明申请

US20090141547A1 Non-volatile memory devices and methods of fabricating and using the same 有权
标题翻译：非易失性存储器件及其制造和使用方法
公开(公告)号：US20090141547A1
公开(公告)日：2009-06-04
申请号：US12149209
申请日：2008-04-29
申请人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
发明人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： G11C5/02 , G11C5/025 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
摘要翻译：提供了一种非易失性存储器件，其可以具有堆叠结构并且可以容易地以增加的密度集成，以及制造和使用非易失性存储器件的方法。非易失性存储器件可以包括至少一对第一电极线。至少一个第二电极线可以在所述至少一对第一电极线之间。至少一个数据存储层可以在至少一对第一电极线和至少一个第二电极线之间，并且可以局部地存储电阻变化。

18. 发明申请

US20090016107A1 Methods of operating nonvolatile memory devices 有权
标题翻译：操作非易失性存储设备的方法
公开(公告)号：US20090016107A1
公开(公告)日：2009-01-15
申请号：US12073314
申请日：2008-03-04
申请人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
发明人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/34
摘要： Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.
摘要翻译：提供了非易失性存储器件的操作方法。在操作包括多个存储单元的非易失性存储器件的方法中，通过在其中记录有记录数据的存储单元的通道上感应升压电压来稳定记录数据。从多个存储单元中选择存储单元，并且所选存储单元的通道上的升压电压由连接到所选存储单元的至少一个存储单元的通道电压引起。

19. 发明申请

US20080315285A1 Non-volatile memory devices and methods of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080315285A1
公开(公告)日：2008-12-25
申请号：US12071452
申请日：2008-02-21
申请人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
发明人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
摘要翻译：提供非易失性存储器件及其制造方法。非易失性存储器件可以包括具有从半导体衬底延伸并且彼此相对的一对侧壁沟道区的半导体衬底，以及在该对侧壁沟道区之间并从半导体衬底突出的浮置栅电极。控制栅电极可以形成在半导体衬底和浮栅电极的一部分上。

20. 发明申请

US20080111199A1 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US20080111199A1
公开(公告)日：2008-05-15
申请号：US11976004
申请日：2007-10-19
申请人： Suk-pil KIM , Yoon-dong Park , Jong-Jin Lee , Won-joo Kim , June-mo Koo , Seung-hwan Song
发明人： Suk-pil KIM , Yoon-dong Park , Jong-Jin Lee , Won-joo Kim , June-mo Koo , Seung-hwan Song
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式