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11. 发明授权

US07071094B2 Dual layer barrier film techniques to prevent resist poisoning 有权
标题翻译：双层阻挡膜技术，以防止中毒
公开(公告)号：US07071094B2
公开(公告)日：2006-07-04
申请号：US10893659
申请日：2004-07-16
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
摘要翻译：本发明提供一种通过在含有氮的第一阻挡层的顶部沉积第二无氮阻挡层来形成阻挡膜以防止半导体器件中的中毒的方法。在第二阻挡层上形成低k电介质层。该技术保持了第一阻挡层的低漏电特性，并且减少随后施加的光致抗蚀剂层的氮中毒。

12. 发明授权

US06812134B1 Dual layer barrier film techniques to prevent resist poisoning 有权
标题翻译：双层阻挡膜技术，以防止中毒
公开(公告)号：US06812134B1
公开(公告)日：2004-11-02
申请号：US09896363
申请日：2001-06-28
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01K214763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
摘要翻译：本发明提供一种通过在含有氮的第一阻挡层的顶部沉积第二无氮阻挡层来形成阻挡膜以防止半导体器件中的中毒的方法。在第二阻挡层上形成低k电介质层。该技术保持了第一阻挡层的低漏电特性，并且减少随后施加的光致抗蚀剂层的氮中毒。

13. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

14. 发明申请

US20060035457A1 Interconnection capacitance reduction 审中-公开
标题翻译：互连电容降低
公开(公告)号：US20060035457A1
公开(公告)日：2006-02-16
申请号：US10915166
申请日：2004-08-10
申请人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.
摘要翻译：对集成电路的制造方法的改进。移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

15. 发明申请

US20060035455A1 Interconnect dielectric tuning 失效
公开(公告)号：US20060035455A1
公开(公告)日：2006-02-16
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

16. 发明授权

US06423630B1 Process for forming low K dielectric material between metal lines 有权
标题翻译：在金属线之间形成低K电介质材料的工艺
公开(公告)号：US06423630B1
公开(公告)日：2002-07-23
申请号：US09704164
申请日：2000-10-31
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Dung-Ching Perng
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Dung-Ching Perng
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： A process is disclosed for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure. The steps include: depositing, over and between the plurality of metal lines, a layer of a first low k dielectric material resistant to via poisoning; then planarizing the layer of first low k dielectric material sufficiently to open voids formed in. the first low k dielectric material between the metal lines; then depositing, over the layer of first low k dielectric material and into the opened voids, a layer of second low k dielectric material capable of filling the opened voids in the layer of first low k dielectric material; and then depositing a layer of a third low k dielectric material resistant to via poisoning over the first low k dielectric material and the voids filled with the second low k dielectric material.
摘要翻译：公开了一种用于在预先形成在集成电路结构的电介质层上的多个间隔开的金属线之间和之上形成低k电介质材料的工艺。所述步骤包括：在所述多个金属线之间和之上沉积耐经过中毒的第一低k电介质材料层; 然后使第一低k电介质材料的层平坦化，以使金属线之间的第一低k电介质材料中形成的空隙开放; 然后在第一低k电介质材料的层上沉积到开放的空隙中，形成能够填充第一低k介电材料层中的开放空隙的第二低介电材料层; 然后在第一低k电介质材料和填充有第二低k电介质材料的空隙中沉积耐经过中毒的第三低k电介质材料层。

17. 发明授权

US5895267A Method to obtain a low resistivity and conformity chemical vapor deposition titanium film 失效
标题翻译：获得低电阻率和一致性化学气相沉积钛膜的方法
公开(公告)号：US5895267A
公开(公告)日：1999-04-20
申请号：US889839
申请日：1997-07-09
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： C23C16/18 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843
摘要： A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.
摘要翻译：描述了通过两阶段沉积工艺形成高度保形的具有高阶梯覆盖和低电阻率的氮化钛阻挡层的方法。氮化钛阻挡层的低温沉积提供高度一致性和良好的阶梯覆盖但具有高电阻率的材料。氮化钛阻挡层的高温沉积产生低电阻率的材料。因此，通过本发明的方法在低温高温下以分离的步骤沉积的氮化钛阻挡层特别适用于特征在于窄和深接触孔的现代密度增加的装置。

18. 发明授权

US06613665B1 Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface 有权
标题翻译：一种用于形成集成电路结构的方法，其包括在上表面具有抗反射特性的低k电介质材料层
公开(公告)号：US06613665B1
公开(公告)日：2003-09-02
申请号：US10002981
申请日：2001-10-26
申请人： Wilbur G. Catabay , Wei-Jen Hsia
发明人： Wilbur G. Catabay , Wei-Jen Hsia
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76807 , H01L21/76826
摘要： A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.
摘要翻译：公开了一种用于形成集成电路结构的方法，其特征在于形成组合的电介质层和抗反射涂层。该方法包括在集成电路结构上形成介电材料层，以及处理介电材料层的表面以在其中形成抗反射涂层（ARC）表面。当然后在ARC表面上形成一层光致抗蚀剂，并且光致抗蚀剂层暴露于辐射图形时，ARC表面提高了光致抗蚀剂层中辐射图案复制的准确性。优选地，用包含元素和/或化合物的离子的等离子体处理介电层的表面以形成ARC表面。

19. 发明授权

US06204192B1 Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures 有权
标题翻译：在集成电路结构中的铜金属化的至少一个低介电常数绝缘层中形成的开口的等离子体清洁工艺
公开(公告)号：US06204192B1
公开(公告)日：2001-03-20
申请号：US09281602
申请日：1999-03-29
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L2100
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/7681 , H01L21/76814 , H01L21/76826
摘要： A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.
摘要翻译：提供了一种用于从集成电路结构的铜金属互连层上去除在低介电常数绝缘材料的一层或多层中形成的一个或多个开口的蚀刻残留物的工艺，其包括清洁铜互连层的表面的暴露部分在一个或多个开口的底部，该方法包括提供各向异性氢等离子体以引起等离子体中的离子与一个或多个开口底部的蚀刻残留物（包括暴露的铜表面上的氧化铜）的化学反应，从而清洁铜表面的暴露部分，并且在不溅射开口底部的铜的情况下除去蚀刻残留物。

20. 发明授权

US6147012A Process for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constant 有权
标题翻译：在抑制压力尖峰并抑制介电常数增加的同时形成低k氧化硅介电材料的方法
公开(公告)号：US6147012A
公开(公告)日：2000-11-14
申请号：US438642
申请日：1999-11-12
申请人： Valeriy Sukharev , Wei-Jen Hsia
发明人： Valeriy Sukharev , Wei-Jen Hsia
IPC分类号： C23C16/40 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/3122 , H01L21/31604 , H01L21/31633
摘要： A process for forming low k silicon oxide dielectric material having a dielectric constant no greater than 3.0, while suppressing pressure spikes during the formation of the low k silicon oxide dielectric material comprises reacting an organo-silane and hydrogen peroxide in a reactor chamber containing a silicon substrate while maintaining an electrical bias on the substrate. In a preferred embodiment the reactants are flowed into the reactor at a reactant flow ratio of organo-silane reactant to hydrogen peroxide reactant of not more than 10.6 sccm of organo-silane reactant per 0.1 grams/minute of hydrogen peroxide reactant; and the substrate is biased with either a positive DC bias potential, with respect to the grounded reactor chamber walls, of about +50 to +300 volts, or a low frequency AC bias potential ranging from a minimum of +50/-50 volts up to a maximum of about +300/-300 volts.
摘要翻译：用于形成介电常数不大于3.0的低k氧化硅电介质材料的工艺，同时在形成低k氧化硅电介质材料期间抑制压力尖峰包括使有机硅烷和过氧化氢在含有硅的反应器室中反应衬底，同时保持衬底上的电偏压。在优选的实施方案中，反应物以有机硅烷反应物与过氧化氢反应物的反应物流量比以每0.1克/分钟的过氧化氢反应物不超过10.6sccm的有机硅烷反应物流入反应器; 并且基板相对于接地的反应器室壁具有大约+50至+300伏特的正DC偏置电位或从+ 50 / -50伏特的最小值的低频AC偏置电位偏置到最大约+ 300 / -300伏特。

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