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11. 发明申请

US20050074051A1 Temperature sensing circuit for use in semiconductor integrated circuit 失效
标题翻译：温度传感电路用于半导体集成电路
公开(公告)号：US20050074051A1
公开(公告)日：2005-04-07
申请号：US10942776
申请日：2004-09-17
申请人： Myung-Gyoo Won , Jae-Hoon Kim , Jong-Wook Park
发明人： Myung-Gyoo Won , Jae-Hoon Kim , Jong-Wook Park
IPC分类号： G11C11/40 , G01K3/00 , G11C7/04 , G01K7/00
CPC分类号： G01K3/005
摘要： A temperature sensing circuit has numerous trip points in conformity with a temperature change without adding decrease resistance branches, so as to obtain a fine control based on the temperature change. Accordingly, when employed in a semiconductor memory device, the temperature sensing circuit substantially reduces the consumption of refresh electrical power in a stand-by state without decreasing the reliability of the semiconductor memory device.
摘要翻译：温度检测电路具有多个温度变化的跳变点，而不增加减少电阻分支，从而获得基于温度变化的精细控制。因此，当采用半导体存储器件时，温度检测电路在不降低半导体存储器件的可靠性的情况下，基本上降低了备用状态下刷新电力的消耗。

12. 发明授权

US5982663A Nonvolatile semiconductor memory performing single bit and multi-bit operations 失效
标题翻译：执行单位和多位操作的非易失性半导体存储器
公开(公告)号：US5982663A
公开(公告)日：1999-11-09
申请号：US10430
申请日：1998-01-21
申请人： Jong-Wook Park
发明人： Jong-Wook Park
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C29/04 , G11C16/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C2211/5641
摘要： The disclosed invention is a nonvolatile memory having a memory field and a redundant field within a single semiconductor chip. The redundant field is used to store essential information regarding device formulation or address mapping. The nonvolatile memory includes a programming circuit capable of programming and verifying a selected memory cell within the redundant field with single-bit data while a selected memory cell within the memory field is being programmed and verified with multi-bit data. The nonvolatile memory also includes a reading circuit capable of reading single-bit data from a selected memory cell within the redundant field while multi-bit data is being read from a selected memory cell within the memory field. Therefore, according to this invention a single-bit operation for the redundant field can be performed without disturbing a multi-bit operation for the memory field.
摘要翻译：所公开的发明是在单个半导体芯片内具有存储器场和冗余场的非易失性存储器。冗余字段用于存储关于设备配方或地址映射的基本信息。非易失性存储器包括编程电路，该编程电路能够利用单位数据编程和验证冗余场内的选定存储单元，同时存储区内的所选存储单元正在使用多位数据进行编程和验证。非易失性存储器还包括读取电路，其能够从冗余字段内的选定存储单元读取单位数据，同时从存储器区域内的所选存储单元读取多位数据。因此，根据本发明，可以在不干扰存储器字段的多位操作的情况下执行冗余字段的单位操作。

13. 发明授权

US5862074A Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating same 失效
标题翻译：具有可重新配置的非易失性多位存储单元的集成电路存储器件及其操作方法
公开(公告)号：US5862074A
公开(公告)日：1999-01-19
申请号：US944876
申请日：1997-10-06
申请人： Jong-Wook Park
发明人： Jong-Wook Park
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5642 , G11C2211/5641 , G11C2211/5642
摘要： Integrated circuit memory devices contain a plurality of nonvolatile memory cells and preferred circuits for selectively configuring the memory cells as multi-bit memory cells having more than two programmable states, during a multi-bit mode of operation, or for configuring the memory cells as single-bit memory cells during a single-bit mode of operation. The preferred circuits contain first and second sense amplifiers that can be electrically coupled to first and second strings of memory cells in the plurality thereof, and a pass transistor for electrically connecting sense nodes of the first and second sense amplifiers together during the multi-bit mode of operation. The first and second sense amplifiers also contain first and second latches, respectively, and the first and second latches each have normal and complementary outputs. The normal outputs of the first and second latches are electrically coupled to first and second input/output lines, respectively. First and second latch control circuits are also provided for enabling the single-bit and multi-bit modes of operation. Here, the single-bit mode of operation (i.e., two-state mode of operation) may be used for high fidelity applications requiring fault-free operation and the multi-bit mode of operation (e.g. four-state mode of operation) may be used for applications involving the storage of mass amounts of information such as audio data, where memory loss or corruption of small amounts of data does not significantly affect the fidelity of the information when read as a whole.
摘要翻译：集成电路存储器件包含多个非易失性存储器单元和用于在多位操作模式期间将存储器单元选择性地配置为具有多于两个可编程状态的多位存储器单元的优选电路，或用于将存储器单元配置为单个在单位操作模式下的位存储单元。优选的电路包含第一和第二读出放大器，其可以电耦合到多个存储单元中的第一和第二串存储器单元;以及传输晶体管，用于在多位模式下将第一和第二读出放大器的感测节点电连接在一起的操作。第一和第二读出放大器还分别包含第一和第二锁存器，并且第一和第二锁存器各自具有正常和互补的输出。第一和第二锁存器的正常输出分别电耦合到第一和第二输入/输出线。还提供了第一和第二锁存器控制电路，用于实现单位和多位操作模式。这里，单位操作模式（即，两状态操作模式）可用于需要无故障操作的高保真应用，并且多位操作模式（例如，四态操作模式）可以是用于存储大量信息（如音频数据）的应用程序，其中存储器丢失或少量数据的损坏在整体读取时不会显着影响信息的保真度。

14. 发明授权

US09281959B2 Method for controlling home network device using universal web application and apparatus thereof 有权
标题翻译：使用通用网络应用控制家庭网络设备的方法及其装置
公开(公告)号：US09281959B2
公开(公告)日：2016-03-08
申请号：US12745003
申请日：2008-11-27
申请人： Ho Jin , Young-Chul Sohn , Jong-Wook Park
发明人： Ho Jin , Young-Chul Sohn , Jong-Wook Park
IPC分类号： G06F15/16 , H04L12/28
CPC分类号： H04L12/2818
摘要： A method of controlling a home network device by using a universal web application. In the method, the universal web application may receive control information, for controlling the home network device, from a server. A control command, which is issued to control the home network device, may be sent to a control point module by using a script application program interface (API) that is included in the received control information. Accordingly, result data that is obtained by executing the control command on the home network device may be received by the control point module.
摘要翻译：一种通过使用通用网络应用来控制家庭网络设备的方法。在该方法中，通用网络应用程序可以从服务器接收用于控制家庭网络设备的控制信息。可以通过使用包含在所接收的控制信息中的脚本应用程序接口（API）将发出控制家庭网络设备的控制命令发送到控制点模块。因此，通过在家庭网络设备上执行控制命令而获得的结果数据可以被控制点模块接收。

15. 发明申请

US20110126271A1 METHOD AND APPARATUS FOR REGISTERING A DEVICE IN ACCESS POINT 有权
标题翻译：用于在接入点中注册设备的方法和装置
公开(公告)号：US20110126271A1
公开(公告)日：2011-05-26
申请号：US13055360
申请日：2009-05-25
申请人： Il-Joo Kim , Jong-Wook Park , Ho Jin , Young-Chul Sohn
发明人： Il-Joo Kim , Jong-Wook Park , Ho Jin , Young-Chul Sohn
IPC分类号： G06F17/30
CPC分类号： H04W12/06 , H04W60/00 , H04W88/08
摘要： Provided is a method of registering an unregistered device in an access point (AP) by using a registered device registered in the AP, the method including: transmitting a control signal for controlling the registered device to the registered device so as to transmit a mode change request, which requests the AP to change a mode to an authentication approval mode approving an authentication operation with the unregistered device, to the AP; transmitting a mode confirm request, which confirms whether an operation mode of the AP is the authentication approval mode, to the AP; receiving a mode confirm response as a response to the mode confirm request from the AP that receives the mode change request; and selectively performing an authentication operation with the AP, based on the received mode confirm response.
摘要翻译：提供了一种通过使用登记在AP中的注册设备在接入点（AP）中注册未注册设备的方法，所述方法包括：向注册设备发送用于控制注册设备的控制信号，以便发送模式改变请求，其请求AP将模式更改为认证认证模式，以批准与未注册设备的认证操作; 向AP发送确认AP的操作模式是否为认证批准模式的模式确认请求; 接收模式确认响应作为对来自接收模式改变请求的AP的模式确认请求的响应; 并且基于所接收的模式确认响应来选择性地执行与所述AP的认证操作。

16. 发明授权

US07724572B2 Integrated circuit having a non-volatile memory cell transistor as a fuse device 失效
标题翻译：具有作为熔丝器件的非易失性存储单元晶体管的集成电路
公开(公告)号：US07724572B2
公开(公告)日：2010-05-25
申请号：US11451441
申请日：2006-06-13
申请人： Jong-Wook Park , Sang-Jae Lee , Myung-Gyoo Won
发明人： Jong-Wook Park , Sang-Jae Lee , Myung-Gyoo Won
IPC分类号： G11C16/06
CPC分类号： G11C29/789 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.
摘要翻译：一种半导体集成电路器件具有可以在不由于使用激光束或电流导致的断裂的情况下电断开的熔丝器件。半导体集成电路器件采用通过制造易失性半导体存储单元阵列的工艺制造的单个多晶硅EEPROM型单元的MOSFET作为用于存储状态信息的熔丝器件。

17. 发明申请

US20090106503A1 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US20090106503A1
公开(公告)日：2009-04-23
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G06F12/14
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

18. 发明申请

US20060245280A1 Integrated circuit having a non-volatile memory cell transistor as a fuse device 失效
标题翻译：具有作为熔丝器件的非易失性存储单元晶体管的集成电路
公开(公告)号：US20060245280A1
公开(公告)日：2006-11-02
申请号：US11451441
申请日：2006-06-13
申请人： Jong-Wook Park , Sang-Jae Lee , Myung-Gyoo Won
发明人： Jong-Wook Park , Sang-Jae Lee , Myung-Gyoo Won
IPC分类号： G11C29/00
CPC分类号： G11C29/789 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.
摘要翻译：一种半导体集成电路器件具有可以在不由于使用激光束或电流导致的断裂的情况下电断开的熔丝器件。半导体集成电路器件采用通过制造易失性半导体存储单元阵列的工艺制造的单个多晶硅EEPROM型单元的MOSFET作为用于存储状态信息的熔丝器件。

19. 发明授权

US07107178B2 Temperature sensing circuit for use in semiconductor integrated circuit 失效
标题翻译：温度传感电路用于半导体集成电路
公开(公告)号：US07107178B2
公开(公告)日：2006-09-12
申请号：US10942776
申请日：2004-09-17
申请人： Myung-Gyoo Won , Jae-Hoon Kim , Jong-Wook Park
发明人： Myung-Gyoo Won , Jae-Hoon Kim , Jong-Wook Park
IPC分类号： G01F15/00 , G01K7/00
CPC分类号： G01K3/005
摘要： A temperature sensing circuit has numerous trip points in conformity with a temperature change without adding decrease resistance branches, so as to obtain a fine control based on the temperature change. Accordingly, when employed in a semiconductor memory device, the temperature sensing circuit substantially reduces the consumption of refresh electrical power in a stand-by state without decreasing the reliability of the semiconductor memory device.
摘要翻译：温度检测电路具有多个温度变化的跳变点，而不增加减少电阻分支，从而获得基于温度变化的精细控制。因此，当采用半导体存储器件时，温度检测电路在不降低半导体存储器件的可靠性的情况下，基本上降低了备用状态下刷新电力的消耗。

20. 发明授权

US08209652B2 Semiconductor device and layout method of decoupling capacitor thereof 有权
标题翻译：半导体器件及其去耦电容器的布局方法
公开(公告)号：US08209652B2
公开(公告)日：2012-06-26
申请号：US12069316
申请日：2008-02-08
申请人： Jong-Wook Park
发明人： Jong-Wook Park
IPC分类号： G06F17/50
CPC分类号： H01L27/0805 , H01L27/0207
摘要： A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in the first direction and in a second direction; a plurality of sub power voltage supplying lines arranged in the second direction in a border of the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines arranged in a net form in the border of the plurality of decoupling capacitor cells, wherein the plurality of decoupling capacitor cells have a first active region arranged to receive the ground voltage and the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor.
摘要翻译：公开了一种半导体器件及其去耦电容器的布局方法。半导体器件包括沿第一方向布置的主电源/接地电压电压线; 多个去耦电容器单元，用于降低由第一方向和第二方向上的电源电压和接地电压产生的功率噪声; 在所述多个解耦电容器单元的边界中沿所述第二方向布置的多个副电源电压供给线; 以及在所述多个去耦电容器单元的边界中以网状布置的多个次地电压供电线，其中所述多个去耦电容器单元具有布置成接收所述接地电压的第一有源区，并且所述第二有源区设置为接收电源电压并避免在去耦电容器中形成反相的区域。

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