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11. 发明授权

US07496169B2 Frequency synthesizer, pulse train generation apparatus and pulse train generation method 失效
标题翻译：频率合成器，脉冲串生成装置和脉冲串生成方法
公开(公告)号：US07496169B2
公开(公告)日：2009-02-24
申请号：US11224803
申请日：2005-09-13
申请人： Kaoru Kanehachi , Akira Toyama
发明人： Kaoru Kanehachi , Akira Toyama
IPC分类号： H03D3/24
CPC分类号： H03L7/0807 , H03K2005/00052 , H03K2005/00156 , H03K2005/00241
摘要： A frequency synthesizer comprises a digital/analog converter which sequentially converts difference data of phase data indicating the phase of a reference signal to an analog value, a voltage signal generator which integrates the analog value converted by the digital/analog converter, thereby generating a voltage signal interpolating between signal levels corresponding to two time-sequential pieces of the phase data, a reference-timing-signal output section which outputs a reference timing signal indicating the specific phase of the reference signal at a timing when the signal level of the voltage signal generated by the voltage signal generator crosses a preset setting voltage, and a reset section which resets the voltage signal generated by the voltage signal generator to the setting voltage. Accordingly, the noise performance of an output signal from the frequency synthesizer is improved.
摘要翻译：频率合成器包括数字/模拟转换器，其顺序地将指示参考信号的相位的相位数据的差分数据转换为模拟值，电压信号发生器将由数字/模拟转换器转换的模拟值积分，从而产生电压在对应于两个时序的相位数据的信号电平之间进行信号内插;参考定时信号输出部，其在电压信号的信号电平的定时输出指示参考信号的特定相位的参考定时信号由电压信号发生器产生的电压跨越预设的设定电压，以及复位部，其将由电压信号发生器产生的电压信号复位为设定电压。因此，提高了来自频率合成器的输出信号的噪声性能。

12. 发明申请

US20060056565A1 Frequency synthesizer, pulse train generation apparatus and pulse train generation method 失效
公开(公告)号：US20060056565A1
公开(公告)日：2006-03-16
申请号：US11224803
申请日：2005-09-13
申请人： Kaoru Kanehachi , Akira Toyama
发明人： Kaoru Kanehachi , Akira Toyama
IPC分类号： H03D3/24
CPC分类号： H03L7/0807 , H03K2005/00052 , H03K2005/00156 , H03K2005/00241
摘要： A frequency synthesizer comprises a digital/analog converter which sequentially converts difference data of phase data indicating the phase of a reference signal to an analog value, a voltage signal generator which integrates the analog value converted by the digital/analog converter, thereby generating a voltage signal interpolating between signal levels corresponding to two time-sequential pieces of the phase data, a reference-timing-signal output section which outputs a reference timing signal indicating the specific phase of the reference signal at a timing when the signal level of the voltage signal generated by the voltage signal generator crosses a preset setting voltage, and a reset section which resets the voltage signal generated by the voltage signal generator to the setting voltage. Accordingly, the noise performance of an output signal from the frequency synthesizer is improved.

13. 发明申请

US20050058190A1 Pulse pattern generating apparatus 失效
标题翻译：脉冲图案生成装置
公开(公告)号：US20050058190A1
公开(公告)日：2005-03-17
申请号：US10897073
申请日：2004-07-23
申请人： Chie Sato , Shinji Kobayashi , Hirotoshi Kodaka , Ikurou Aoki , Kousuke Doi , Akira Toyama , Morio Wada , Hiroyuki Matsuura , Hiroshi Sugawara , Masamichi Ohashi , Hironori Okita , Yasukazu Akasaka , Tsuyoshi Yakihara , Akira Miura
发明人： Chie Sato , Shinji Kobayashi , Hirotoshi Kodaka , Ikurou Aoki , Kousuke Doi , Akira Toyama , Morio Wada , Hiroyuki Matsuura , Hiroshi Sugawara , Masamichi Ohashi , Hironori Okita , Yasukazu Akasaka , Tsuyoshi Yakihara , Akira Miura
IPC分类号： G01R31/319 , H03K3/84 , H04L25/02 , H04B17/00
CPC分类号： G01R31/3171 , G01R31/31928
摘要： An object of this invention is to realize a pulse pattern generating apparatus that outputs a test signal of high waveform quality even when the shape of an eye pattern is changed. This invention is an improvement of a pulse pattern generating apparatus that generates a test signal of a predetermined pattern by using plural digital-analog converters and outputs the test signal to a test subject. The apparatus includes: a parameter setting unit for setting values of plural parameters that determine the shape of an eye pattern of the test signal; a storage unit for storing output values to the digital-analog converters corresponding to the values of the parameters; an arithmetic operation unit for calculating output values to the digital-analog converters from the values of the parameters from the parameter setting unit and the output values in the storage unit; and a voltage value setting unit for setting, for the digital-analog converters, voltage values to be outputted from the digital-analog converters on the basis of the result of calculation by the arithmetic operation unit.
摘要翻译：本发明的一个目的是实现即使当眼图的形状改变时也输出高波形质量的测试信号的脉冲图形生成装置。本发明是通过使用多个数模转换器生成预定模式的测试信号并将测试信号输出给测试对象的脉冲图案生成装置的改进。该装置包括：参数设置单元，用于设置确定测试信号的眼图的形状的多个参数的值; 存储单元，用于根据参数的值存储对数模转换器的输出值; 算术运算单元，用于根据来自参数设定单元的参数值和存储单元中的输出值计算出数字模拟转换器的输出值; 以及电压值设定单元，用于根据算术运算单元的计算结果，对数模转换器设定从数模转换器输出的电压值。

14. 发明授权

US06551188B2 Video game device, new practice creating method and readable storage medium storing new practice creating program 有权
标题翻译：视频游戏设备，新练习创建方法和存储新练习创建程序的可读存储介质
公开(公告)号：US06551188B2
公开(公告)日：2003-04-22
申请号：US09837068
申请日：2001-04-18
申请人： Akira Toyama , Toshimitsu Aoki , Hiroshi Tanibuchi
发明人： Akira Toyama , Toshimitsu Aoki , Hiroshi Tanibuchi
IPC分类号： A63F924
CPC分类号： A63F13/67 , A63F13/10 , A63F13/69 , A63F13/828 , A63F2300/65 , A63F2300/8011 , A63F2300/8052
摘要： A player is able to train a game character in a strategic manner, and hence a game generating a high degree of interest can be executed. Practice feature names of plural types are displayed in a list on a monitor 22 by means of basic practice feature display 113, and one practice feature name is selected by moving and displaying a cursor over one practice feature name of the displayed practice feature names, by means of cursor movement display 112, and furthermore, item names of plural types are displayed in a list on the monitor 22 by means of item display 114, and one item name is selected by moving and displaying a cursor over one item name of the displayed item names, by means of cursor movement display 112, whereby a new practice is created by a new practice creating device.
摘要翻译：玩家能够以战略的方式训练游戏角色，因此可以执行高度兴趣的游戏。通过基本练习特征显示器113在监视器22上的列表中显示多种类型的练习功能名称，并且通过在显示的练习特征名称的一个练习特征名称上移动和显示光标来选择一个练习特征名称，通过光标移动显示器112的装置，此外，通过项目显示114在监视器22上的列表中显示多种类型的项目名称，并且通过将光标移动并显示在所显示的一个项目名称上来选择一个项目名称项目名称，通过光标移动显示112，由此由新的练习创建设备创建新练习。

15. 发明授权

US06369731B1 Delta sigma D/A converter 有权
标题翻译： Delta sigma D / A转换器
公开(公告)号：US06369731B1
公开(公告)日：2002-04-09
申请号：US09724170
申请日：2000-11-28
申请人： Minoru Takeda , Yoshihiro Hanada , Akira Toyama
发明人： Minoru Takeda , Yoshihiro Hanada , Akira Toyama
IPC分类号： H03M166
CPC分类号： H03M7/3006 , H03M7/3042
摘要： The problem of the present invention is, in a plural-number order delta sigma D/A converter, not to cause click noise upon performing mute operation at no-signal input idling and hence to eliminate the necessity of a circuit for removing this. In order to perform sequence operation for rendering zero an output signal by lowering the order of a loop filter in order when stopping the operation of a plural-number order delta sigma D/A converter, 1st-order differentiators corresponding to each order and switch means for rendering inputs to these 1st-order differentiators zero are provided in the loop filter.
摘要翻译：本发明的问题是在多数量级的Σ-ΔD/ A转换器中，在无信号输入空闲时进行静音操作时不会产生点噪，因此消除了用于去除该信号的电路的必要性。为了执行顺序操作，以通过在停止多个数量级Σ-ΔD/ A转换器的操作时按顺序降低环路滤波器的次序来对输出信号进行零归零，对应于每个顺序的一阶微分器和用于在循环滤波器中提供了对这些一阶微分器零点的渲染输入。

16. 发明授权

US5727085A Waveform data compression apparatus 失效
标题翻译：波形数据压缩装置
公开(公告)号：US5727085A
公开(公告)日：1998-03-10
申请号：US528457
申请日：1995-09-14
申请人： Akira Toyama , Kazuhiko Hakuta , Masayoshi Nakamura , Masataka Saito
发明人： Akira Toyama , Kazuhiko Hakuta , Masayoshi Nakamura , Masataka Saito
IPC分类号： G10L19/00 , G06T9/00 , G10L19/14 , H03M7/38 , G06K9/36
CPC分类号： G10L19/16 , G06T9/004
摘要： In an APC system waveform dam compression apparatus which generates an optimum prediction coefficient utilizing a block calculation process in a first mode and generating prediction data utilizing a block calculation process based on this optimum prediction coefficient in a second mode with respect to a fixed number of blocked waveform data, to make possible use of suitable data in the first prediction calculation process of each block calculation process. A data holding section for holding data corresponding to at least final first waveform data to be used in a final prediction calculation process of a block calculation process in a second mode, and a first selection section for using data held in the data holding section in place of data memorized in a second delay section in each first prediction calculation process of each block calculation process of the next block are provided in an operating circuit.
摘要翻译：在APC系统波形坝压缩装置中，利用第一模式中的块计算处理产生最佳预测系数，并且利用第二模式中基于该最佳预测系数的块计算处理相对于固定数量的阻塞产生预测数据波形数据，以便在每个块计算过程的第一预测计算过程中可能使用合适的数据。数据保持部分，用于保存对应于要在第二模式中的块计算处理的最终预测计算处理中使用的至少最终的第一波形数据的数据;以及第一选择部分，用于将数据保存部分中保存的数据使用到位在下一个块的每个块计算处理的每个第一预测计算处理中的第二延迟部中存储的数据被提供在操作电路中。

17. 发明授权

US5481267A Sampling rate converter 失效
标题翻译：采样率转换器
公开(公告)号：US5481267A
公开(公告)日：1996-01-02
申请号：US176560
申请日：1994-01-03
申请人： Satoru Miyabe , Akira Toyama , Minoru Takeda
发明人： Satoru Miyabe , Akira Toyama , Minoru Takeda
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , H04B14/04 , H03M7/00
CPC分类号： H03H17/0628
摘要： A sampling rate converter for converting a first signal having a first sampling rate to a second signal having a second sampling rate, includes a circuit for generating first data corresponding to the ratio of the second sampling rate to the first sampling rate. A second circuit generates second data by correcting the first data with corrective data. A third circuit generates third data corresponding to an estimated output timing of the second signal based upon the second data. A comparator compares the third data with a fourth data corresponding to the actual output timing of the second signal to generate comparative data. A corrective circuit is responsive to the comparative data to generate the corrective data. A further circuit is responsive to the first and third data for generating the second signal.
摘要翻译：用于将具有第一采样率的第一信号转换为具有第二采样率的第二信号的采样率转换器包括用于产生对应于第二采样率与第一采样率的比率的第一数据的电路。第二电路通过用纠正数据校正第一数据来产生第二数据。第三电路基于第二数据产生与第二信号的估计输出定时对应的第三数据。比较器将第三数据与对应于第二信号的实际输出定时的第四数据进行比较，以产生比较数据。校正电路响应于比较数据以产生校正数据。另一电路响应于第一和第三数据用于产生第二信号。

18. 发明申请

US20140073416A1 GAME OPERATION DEVICE, GAME OPERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND GAME OPERATION SYSTEM 有权
标题翻译：游戏操作装置，游戏操作方法，计算机可读记录介质和游戏操作系统
公开(公告)号：US20140073416A1
公开(公告)日：2014-03-13
申请号：US14115443
申请日：2012-05-08
申请人： Akira Toyama
发明人： Akira Toyama
IPC分类号： A63F13/12
CPC分类号： A63F13/792 , A63F13/822 , G07F17/3251
摘要： A deposit managing unit 22 receives a game player's deposit command transmitted from a terminal device 12 and deposits virtual currency in a deposit amount specified by the game player according to the received deposit command. In addition, the deposit managing unit 22 prohibits the game player from using the virtual currency deposited by the game player until a predetermined deposit period expires. When a depositing game player deposits virtual currency, a benefit offering unit 24 offers the depositing game player a benefit that gives a higher advantage to the depositing game player in battle until the deposit period expires in comparison to a case where the depositing game player does not deposit virtual currency.
摘要翻译：存款管理单元22接收从终端设备12发送的游戏者的存款命令，并根据接收到的存款命令存入游戏玩家指定的存款金额的虚拟币种。此外，存款管理单元22禁止游戏玩家使用游戏玩家存放的虚拟货币，直到预定的存款期限到期。当存款游戏玩家存放虚拟货币时，利益提供单元24为存款游戏玩家提供了一种利益，其给存款游戏玩家在战斗中具有更高的优势，直到存款期限到期为止，与存款游戏玩家不同存入虚拟货币。

19. 发明授权

US07667544B2 Clock reproducing apparatus 失效
标题翻译：时钟重放装置
公开(公告)号：US07667544B2
公开(公告)日：2010-02-23
申请号：US11649798
申请日：2007-01-05
申请人： Hiroshi Sugawara , Toshimichi Suzuki , Shigeo Uneme , Shinji Iio , Akira Miura , Tadashige Fujita , Akira Toyama , Katsuya Ikezawa , Hirotoshi Kodaka , Sadaharu Oka , Chie Sato
发明人： Hiroshi Sugawara , Toshimichi Suzuki , Shigeo Uneme , Shinji Iio , Akira Miura , Tadashige Fujita , Akira Toyama , Katsuya Ikezawa , Hirotoshi Kodaka , Sadaharu Oka , Chie Sato
IPC分类号： H03K3/03
CPC分类号： H04L7/027 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K2005/00032 , H04L7/0087 , H04L7/0276
摘要： A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, and supplying a phase control signal to the gated oscillator based on the comparison result so as to set a delay time, input data is input to a reset input terminal of the gated oscillator, and different route of the two routes of the oscillating circuit operates depending on a case where the input data is “H” and a case where the input data is “L”.
摘要翻译：时钟再现装置包括：时钟再现电路，具有：门控振荡器，具有两条路线的振荡电路; 以及频率控制电路，用于将门控振荡器的输出的相位与参考时钟的相位进行比较，并且基于比较结果将相位控制信号提供给门控振荡器，以便设置延迟时间，输入数据是输入到门控振荡器的复位输入端子，并且根据输入数据为“H”的情况和输入数据为“L”的情况，振荡电路的两条路线的不同路线工作。

20. 发明授权

US07243033B2 Inspection apparatus 失效
标题翻译：检验仪器
公开(公告)号：US07243033B2
公开(公告)日：2007-07-10
申请号：US11180905
申请日：2005-07-14
申请人： Chie Sato , Yusuke Kishine , Tetsuya Ohtani , Minoru Akutsu , Hiroshi Sugawara , Akira Toyama , Hirotoshi Kodaka , Katsuya Ikezawa , Shinji Kobayashi , Akira Miura
发明人： Chie Sato , Yusuke Kishine , Tetsuya Ohtani , Minoru Akutsu , Hiroshi Sugawara , Akira Toyama , Hirotoshi Kodaka , Katsuya Ikezawa , Shinji Kobayashi , Akira Miura
IPC分类号： G01R13/00
CPC分类号： G01R13/029
摘要： An inspection apparatus inspects an inspected object based on a waveform quality of a signal that the inspected object outputs. The inspection apparatus has a power supply section which outputs a control signal that controls an output of the inspected object, a waveform measuring section which measures the signal that the inspected object outputs to generate a waveform image, an analyzing section which derives a value indicating a waveform quality from the waveform image that the waveform measuring section measures, a deciding section which decides whether or not the value derived by the analyzing section satisfies a target value, and an optimizing section which changes a set value of the control signal that the power supply section outputs, based on a decision result of the deciding section.
摘要翻译：检查装置根据检查对象输出的信号的波形质量来检查被检查物体。检查装置具有输出控制被检查对象的输出的控制信号的电源部，测量被检查对象输出的信号以生成波形图像的波形测量部，分析部，其导出表示来自波形测量部测量的波形图像的波形质量;判定部，判定由分析部导出的值是否满足目标值;优化部，其将控制信号的设定值改变为电源基于决定部分的决策结果。

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