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    • 18. 发明授权
    • Timing jitter frequency detector for timing recovery systems
    • 定时恢复系统的定时抖动频率检测器
    • US06640194B2
    • 2003-10-28
    • US10001649
    • 2001-10-31
    • James M. LittleHiroshi TakatoriScott Chiu
    • James M. LittleHiroshi TakatoriScott Chiu
    • G01R1300
    • H03L7/093H03L7/091
    • A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.
    • 频率检测器包括限幅器,用于根据比较阈值接收和切片相位误差。 限幅器基于相对于比较阈值切片的相位误差产生符号。 如果产生的符号与最后一个符号相同,则提供符号计数器来增加符号计数。 如果符号与最后一个符号不同,则逻辑电路将符号计数与符号计数限制进行比较。 如果符号计数小于符号计数限制,逻辑电路会增加一个高计数器并清除一个低计数器。 如果符号数大于符号计数限制,逻辑电路会递增低计数器并清除高计数器。 提供组合逻辑电路,用于基于符号计数,高计数器和低计数器中的至少一个产生高频抖动真实信号或高频抖动假信号。
    • 19. 发明授权
    • Phase-locked loop timing recovery circuit
    • 锁相环定时恢复电路
    • US5581585A
    • 1996-12-03
    • US327184
    • 1994-10-21
    • Hiroshi TakatoriDaniel L. RayKenneth G. ButtleJames W. Everitt
    • Hiroshi TakatoriDaniel L. RayKenneth G. ButtleJames W. Everitt
    • H04L7/00H04L7/02H04L7/033H04L25/03H03H7/30H03D3/24
    • H04L25/03057H04L7/0058H04L7/0062H04L7/0083
    • A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.
    • 一种定时恢复装置,用于从多级或部分响应码中的稀疏定时信息中恢复定时。 定时恢复装置包括用于根据可选采样率对输入线路码信号进行采样的开关,用于滤波采样信号的前馈均衡器,用于消除滤波信号中的码间干扰的判决反馈均衡器,以及用于恢复滤波信号中的定时 采样信号。 定时恢复电路响应于从前馈均衡器接收的信号创建相位校正信号,从而控制采样开关的采样率,使得决定之前的节点处的信噪比最大化。 通过使用第二相位检测器将压控晶体振荡器控制在一定频率范围内,该第二相位检测器将控制输入线路码的采样的信号的相位与参考时钟进行比较。