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11. 发明申请

US20080094903A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20080094903A1
公开(公告)日：2008-04-24
申请号：US11873859
申请日：2007-10-17
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

12. 发明授权

US08630116B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08630116B2
公开(公告)日：2014-01-14
申请号：US13633553
申请日：2012-10-02
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

13. 发明授权

US08089818B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08089818B2
公开(公告)日：2012-01-03
申请号：US12580795
申请日：2009-10-16
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
CPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.
摘要翻译：一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及存储单元连接在第一和第二线之间。该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。存储单元通过连接到从MAT中选择的每个第一行形成页面。该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

14. 发明申请

US20110128775A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US20110128775A1
公开(公告)日：2011-06-02
申请号：US13024926
申请日：2011-02-10
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

15. 发明申请

US20090237979A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US20090237979A1
公开(公告)日：2009-09-24
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体或存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

16. 发明申请

US20090174032A1 RESISTANCE CHANGE MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：US20090174032A1
公开(公告)日：2009-07-09
申请号：US12351212
申请日：2009-01-09
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
IPC分类号： H01L29/00
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/24
摘要： A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring, a second wiring crossing with the first wiring, and a variable resistance element connected at an intersection of the both wirings; a reading/writing/driving circuit formed on the semiconductor substrate under the three dimensional cell array; a first via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the first wiring in each layer to the reading/writing/driving circuit is formed; and a second via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the second wiring in each layer to the reading/writing/driving circuit is formed. When the first wiring is longer than the second wiring, the number of via arrangements in the first via region is set larger than that in the second via region.
摘要翻译：电阻变化存储器件包括：半导体衬底; 由半导体衬底上的二维排列的多个单元阵列块形成的三维单元阵列，所述单元阵列块通过堆叠多个单元阵列而形成，所述单位阵列包括第一布线，与所述第一布线交叉的第二布线布线和连接在两条布线的交点处的可变电阻元件; 在三维单元阵列下形成在半导体衬底上的读/写/驱动电路; 布置在单元阵列块的端部中的第一通孔区域，其中形成用于将每层中的第一布线连接到读/写/驱动电路的通孔布线; 以及布置在单元阵列块的端部中的第二通孔区域，并且其中形成用于将每层中的第二布线连接到读/写/驱动电路的通孔布线。当第一布线长于第二布线时，第一通孔区域中的通孔布置的数量被设置为大于第二通孔区域中的通孔布置的数量。

17. 发明授权

US07518922B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US07518922B2
公开(公告)日：2009-04-14
申请号：US11749214
申请日：2007-05-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
发明人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2211/5646 , G11C2211/5647
摘要： A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
摘要翻译： NAND型闪速存储器，包括由以矩阵形状排列的多个电子可重写存储单元组成的存储单元阵列;以及数据反转控制单元，判定“1”数据或“0”数据的极性是否为当数据被发送到同时写入数据单元内的多个存储单元时，基于“1”数据和“0”数据的数字被反转，并且反转数据，并且在发送的情况下到存储单元阵列向显示极性反转的数据添加反转标志位。

18. 发明授权

US08379432B2 Nonvolatile semiconductor storage device and data writing method therefor 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US08379432B2
公开(公告)日：2013-02-19
申请号：US13415953
申请日：2012-03-09
申请人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.
摘要翻译：非易失性半导体存储装置包括第一和第二相交线; 在第一第二配线的交点处配置的电可重写存储单元串联连接，包括用于以非易失性方式存储电阻值作为数据的可变电阻器和整流装置; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程，向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。

19. 发明授权

US08154908B2 Nonvolatile semiconductor storage device and data writing method therefor 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US08154908B2
公开(公告)日：2012-04-10
申请号：US13024926
申请日：2011-02-10
申请人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

20. 发明授权

US07907436B2 Nonvolatile semiconductor storage device and data writing method therefor 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US07907436B2
公开(公告)日：2011-03-15
申请号：US12370111
申请日：2009-02-12
申请人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

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