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11. 发明申请

US20050134533A1 Sustain driver, sustain control system, and plasma display 有权
标题翻译：维持驱动器，维持控制系统和等离子显示器
公开(公告)号：US20050134533A1
公开(公告)日：2005-06-23
申请号：US10991243
申请日：2004-11-17
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： G09G3/20 , G09G3/291 , G09G3/294 , G09G3/296 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H03K17/687 , G09G3/28
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

12. 发明申请

US20090108434A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PDP DRIVER, AND PLASMA DISPLAY PANEL 有权
标题翻译：半导体集成电路器件，PDP驱动器和等离子体显示面板
公开(公告)号：US20090108434A1
公开(公告)日：2009-04-30
申请号：US12067953
申请日：2007-03-22
申请人： Eisaku Maeda , Hiroshi Ando , Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga
发明人： Eisaku Maeda , Hiroshi Ando , Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L24/06 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/4911 , H01L2224/49111 , H01L2224/49113 , H01L2224/4917 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.
摘要翻译：在本发明的半导体集成电路器件中，即使导电线彼此短路，也可以抑制接合线的温度升高，提高半导体集成电路器件的可靠性。用于向外部电源供电的半导体集成电路芯片的电源部分的树脂封装的导电引线通过多根接合线与半导体集成电路芯片的接合焊盘连接。此外，连接到用于向半导体集成电路芯片的电源部分提供接地电位的GND的导电引线通过多个接合线与半导体集成电路芯片的接合焊盘连接。

13. 发明申请

US20080068368A1 Sustain Driver, Sustain Control System, And Display Device 有权
标题翻译：维持驱动器，维护控制系统和显示设备
公开(公告)号：US20080068368A1
公开(公告)日：2008-03-20
申请号：US11941240
申请日：2007-11-16
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： G09G3/28 , G09G5/00
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译：双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

14. 发明授权

US07495296B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07495296B2
公开(公告)日：2009-02-24
申请号：US11139590
申请日：2005-05-31
申请人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
发明人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
IPC分类号： H01L29/94
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.
摘要翻译：本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路，驱动器，使得每个单元排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度，第二电平移位电路和预驱动器对应于低侧晶体管的单元宽度。

15. 发明申请

US20070268059A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20070268059A1
公开(公告)日：2007-11-22
申请号：US11749266
申请日：2007-05-16
申请人： Tomohisa SAKAGUCHI , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Eisaku Maeda
发明人： Tomohisa SAKAGUCHI , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Eisaku Maeda
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A semiconductor integrated circuit device capable of securely preventing the output from becoming indefinite even when power is turned ON or OFF or even in a transient state in which the power voltage varies abruptly. In the semiconductor integrated circuit device, a protection circuit compares the power voltage from a first power supply terminal with a reference voltage, detects power ON, power OFF and abrupt power voltage variation, and outputs a reset command signal so that the output at the output terminal has a high impedance at the time of power ON, power OFF and abrupt power voltage variation.
摘要翻译：即使电源接通或断开，或即使在电源电压突然变化的过渡状态下，也能够可靠地防止输出变得不确定的半导体集成电路器件。在半导体集成电路装置中，保护电路将来自第一电源端子的电源电压与参考电压进行比较，检测电源接通，断电和突然的电源电压变化，并输出复位指令信号，使得输出端端子在电源接通，电源关闭和突然的电源电压变化时具有高阻抗。

16. 发明申请

US20050263910A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050263910A1
公开(公告)日：2005-12-01
申请号：US11139590
申请日：2005-05-31
申请人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
发明人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
IPC分类号： H01L23/528 , H01L27/118 , H01L23/52
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize the output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of the cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, where a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.
摘要翻译：本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路，驱动器，使得每个单元格排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度为第二电平移位电路和预驱动器对应于低侧晶体管的单元宽度。

17. 发明申请

US20070273412A1 Drive voltage supply circuit 有权
标题翻译：驱动电源电路
公开(公告)号：US20070273412A1
公开(公告)日：2007-11-29
申请号：US11802635
申请日：2007-05-24
申请人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： H03B1/00
CPC分类号： G09G3/296 , G09G3/293 , G09G2310/0275 , G09G2330/06
摘要： A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.
摘要翻译：驱动电压供给电路具有第一有线线路，第二线路线路，第一驱动电路，多个第二驱动电路，用于驱动第一驱动电路和多个第二驱动电路的控制电路，以及连接有阻抗元件的阻抗元件在第一线路和每个输出端子之间。

18. 发明授权

US08068102B2 Drive voltage supply circuit 有权
标题翻译：驱动电源电路
公开(公告)号：US08068102B2
公开(公告)日：2011-11-29
申请号：US11802635
申请日：2007-05-24
申请人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： G06F3/038 , H03L5/00
CPC分类号： G09G3/296 , G09G3/293 , G09G2310/0275 , G09G2330/06
摘要： A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.
摘要翻译：驱动电压供给电路具有第一有线线路，第二线路线路，第一驱动电路，多个第二驱动电路，用于驱动第一驱动电路和多个第二驱动电路的控制电路，以及连接有阻抗元件的阻抗元件在第一线路和每个输出端子之间。

19. 发明申请

US20090302347A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090302347A1
公开(公告)日：2009-12-10
申请号：US11919504
申请日：2006-09-29
申请人： Hiroki Matsunaga , Masahiko Sasada , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Hiroki Matsunaga , Masahiko Sasada , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： H01L27/04 , H01L29/861
CPC分类号： H01L27/0207 , G09G3/296 , G09G2310/0289 , G09G2330/04 , H01L24/05 , H01L27/0251 , H01L27/0629 , H01L27/11803 , H01L2224/05554 , H01L2924/01004 , H01L2924/13055 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.
摘要翻译：半导体集成电路包括多个电路单元，每个电路单元包括半导体芯片上的焊盘。每个电路单元包括高侧晶体管，电平移位电路，低侧晶体管，预驱动器和焊盘。高侧晶体管和低侧晶体管被布置成彼此面对，垫间插入其间。

20. 发明申请

US20090045480A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090045480A1
公开(公告)日：2009-02-19
申请号：US12094499
申请日：2006-11-07
申请人： Hiroki Matsunaga , Naoki Hishikawa , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Hiroki Matsunaga , Naoki Hishikawa , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L27/12
摘要： A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect.
摘要翻译：半导体集成电路包括半导体芯片上的多个电路单元。多个电路单元沿半导体芯片的第一芯片侧形成。多个电路单元中的每一个具有衬垫。半导体集成电路还包括形成在多个电路单元上的高压电位互连。高压电位互连具有从高压电位互连的中心部分到端部的长度方向上的宽度。

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