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11. 发明申请

US20050106830A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050106830A1
公开(公告)日：2005-05-19
申请号：US11004786
申请日：2004-12-03
申请人： Mika Shiiki , Hiroaki Takasu
发明人： Mika Shiiki , Hiroaki Takasu
IPC分类号： H01L27/04 , H01L21/822 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12 , H01L21/20
CPC分类号： H01L27/0802 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.
摘要翻译：提供了具有精确的分压比，电阻值的小的温度系数和高精度的泄放电阻电路，以及使用具有高精度和小的温度系数的这种泄放电阻电路的半导体器件，作为电压检测器或电压调节器。在使用薄膜电阻器的泄放电阻电路中，使位于薄膜电阻器上方和下方的导体具有与薄膜电阻器基本相同的电位。此外，当多晶硅用于薄膜电阻器时，多晶硅薄膜电阻器的膜厚减薄，并且引入到多晶硅薄膜电阻器中的杂质被制成P型。因此，电阻值的变化被抑制，电阻值的温度依赖性变小。

12. 发明授权

US06586282B1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06586282B1
公开(公告)日：2003-07-01
申请号：US09569182
申请日：2000-05-11
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L2182
CPC分类号： H01L27/0207 , H01L23/5258 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device comprises forming a thin film over a semiconductor substrate, patterning the thin film to define a portion of a laser trimming registration position pattern while simultaneously forming a fuse element formed from the same thin film and separate from the portion of the laser trimming position registration pattern, and forming a metallic film on the portion of the laser trimming position pattern but not on the fuse element.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成薄膜，对薄膜进行构图以限定激光修整对准位置图案的一部分，同时形成由相同薄膜形成的熔丝元件，并与激光修整位置对准图案，并且在激光修整位置图案的部分上形成金属膜，但不在熔丝元件上。

13. 发明授权

US06204836B1 Display device having defect inspection circuit 失效
标题翻译：具有缺陷检查电路的显示装置
公开(公告)号：US06204836B1
公开(公告)日：2001-03-20
申请号：US08239730
申请日：1994-05-09
申请人： Tsuneo Yamazaki , Kunihiro Takahashi , Hiroaki Takasu , Atsushi Sakurai
发明人： Tsuneo Yamazaki , Kunihiro Takahashi , Hiroaki Takasu , Atsushi Sakurai
IPC分类号： G09G336
CPC分类号： G09G3/006 , G09G3/3677 , G09G3/3688 , G09G2310/0281 , G09G2330/12
摘要： A dense display may be provided with an internal defect detection circuit to enhance production yield. A plurality of pixels, each including thin film transistors and liquid crystal cells driven by driving electrodes, are arranged in a matrix form and scanned by a plurality of control signal lines and a plurality of image signal lines. A control signal line driving circuit is formed of shift registers having one bit per signal line, and sample-and-hold circuits. An inspection circuit is provided with plural switching elements, each having a first terminal connected to a respective image signal line, a second terminal connected to an inspection output line and a third terminal receptive of an inspection control input signal for controlling an electrical connection between the first and second terminals. In accordance with this configuration, inspection of individual signal lines may be achieved and the inspection control input signal may be internally or externally generated. Moreover, similar detection circuitry may be used to detect defects in the control signal lines and, in this manner, defects may be located to the individual pixel level.
摘要翻译：密集显示器可以设置有内部缺陷检测电路，以提高产量。多个像素，每个包括薄膜晶体管和由驱动电极驱动的液晶单元，以矩阵形式布置并被多个控制信号线和多个图像信号线扫描。控制信号线驱动电路由每个信号线一位的移位寄存器和采样保持电路构成。一个检查电路设置有多个开关元件，每个开关元件具有连接到相应图像信号线的第一端子，连接到检查输出线的第二端子和接受检查控制输入信号的第三端子，用于控制第第一和第二终端。根据该结构，可以实现各个信号线的检查，并且检查控制输入信号可以在内部或外部产生。此外，类似的检测电路可以用于检测控制信号线中的缺陷，并且以这种方式，可以将缺陷定位到各个像素级。

14. 发明授权

US5602408A Semiconductor device having polycrystalline silicon load devices 失效
标题翻译：具有多晶硅负载装置的半导体装置
公开(公告)号：US5602408A
公开(公告)日：1997-02-11
申请号：US419356
申请日：1995-04-10
申请人： Hitomi Watanabe , Hiroaki Takasu
发明人： Hitomi Watanabe , Hiroaki Takasu
IPC分类号： H01L27/04 , H01L21/822 , H01L27/11 , H01L23/62
CPC分类号： H01L27/1112
摘要： A semiconductor device comprises a silicon semiconductor substrate and an insulating film formed on a surface of the silicon semiconductor substrate. One of a surface of the silicon semiconductor substrate or a surface of the insulating film is provided with at least one step portion. A polycrystalline silicon layer is formed uniformly on at least a side surface of the step portion and a top surface of the insulating film. The polycrystalline silicon layer which is formed on the side surface of the step portion comprises a resistance element, and a portion of the polycrystalline silicon layer which is formed on the top surface of the insulating film is doped with an impurity to form a conductive element. By this construction, the area occupied by the load devices on the semiconductor substrate is effectively reduced, thereby increasing the packing density of the semiconductor device.
摘要翻译：半导体器件包括硅半导体衬底和形成在硅半导体衬底的表面上的绝缘膜。硅半导体基板的表面或绝缘膜的表面之一设置有至少一个台阶部。在台阶部的至少一个侧面和绝缘膜的上表面上均匀地形成多晶硅层。形成在台阶部分的侧面上的多晶硅层包括电阻元件，并且在绝缘膜的顶表面上形成的多晶硅层的一部分被掺杂以形成导电元件。通过这种结构，半导体衬底上的负载装置所占据的面积被有效地减少，从而提高了半导体器件的堆积密度。

15. 发明授权

US5534722A Insulator substrate for a light valve device having an electrostatic protection region 失效
标题翻译：具有静电保护区域的光阀装置的绝缘体基板
公开(公告)号：US5534722A
公开(公告)日：1996-07-09
申请号：US206768
申请日：1994-03-07
申请人： Hiroaki Takasu , Kunihiro Takahashi , Tsuneo Yamazaki
发明人： Hiroaki Takasu , Kunihiro Takahashi , Tsuneo Yamazaki
IPC分类号： H01L27/06 , G02F1/1362 , H01L21/822 , H01L27/04 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/86 , H01L27/01 , H01L23/62
CPC分类号： G02F1/13454 , H01L27/1203 , G02F1/136204
摘要： A semiconductor on insulator substrate has improved electrostatic performance without sacrificing the performance of commonly integrated high-speed integrated circuitry. The semiconductor on insulator substrate includes a single crystal semiconductor thin film having an integrated circuit region and an electrostatic protection region. The thickness of the single crystal semiconductor thin film is greater in the electrostatic protection region than in the integrated circuit region to thereby allow high-speed operation of devices formed in the integrated circuit region. Such a substrate has particular application as a driving substrate for a light valve. In such a device, the integrated circuit region includes thin film switching transistors for selectively applying a voltage to the liquid crystal layer and thin film driving transistors for driving the thin film switching transistors. The electrostatic protection region includes an electrostatic protection device electrically connected to the integrated circuit region, and the electrostatic protection device is effective to protect the driving transistors from exposure to an excess of electrostatic charge.
摘要翻译：绝缘体上半导体衬底具有改进的静电性能，而不牺牲普通集成的高速集成电路的性能。绝缘体上半导体衬底包括具有集成电路区域和静电保护区域的单晶半导体薄膜。静电保护区域中的单晶半导体薄膜的厚度大于集成电路区域的厚度，从而允许在集成电路区域中形成的器件的高速操作。这种基板具有作为光阀的驱动基板的特殊应用。在这种器件中，集成电路区域包括用于选择性地向液晶层施加电压的薄膜开关晶体管和用于驱动薄膜开关晶体管的薄膜驱动晶体管。静电保护区域包括电连接到集成电路区域的静电保护装置，并且静电保护装置有效地保护驱动晶体管不被暴露于过量的静电电荷。

16. 发明授权

US08587051B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08587051B2
公开(公告)日：2013-11-19
申请号：US13374142
申请日：2011-12-13
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region.
摘要翻译：提供了一种电可擦除和可编程的非易失性半导体存储器件，其在漏极区域中形成的隧道区域具有第二导电型低杂质浓度区域，其中第一隧道绝缘膜仅用于注入设置在其上的电子，并且第一导电型具有第二隧道绝缘膜的低杂质浓度区域，用于仅喷射设置在其上的电子，两个区域固定为与漏极区域相同的电位，并且具有比漏极区域更低的杂质浓度。

17. 发明授权

US08575679B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08575679B2
公开(公告)日：2013-11-05
申请号：US13374281
申请日：2011-12-20
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region.
摘要翻译：提供了具有隧道区域的电可擦除和可编程的非易失性半导体存储器件; 隧道区域和隧道区域的周边被挖掘下来，并且通过耗尽电极绝缘膜将给予仲裁电位以耗尽隧道区域的一部分的耗尽电极布置在下降的漏区。

18. 发明授权

US08465999B2 Manufacturing method for image sensor IC 有权
标题翻译：图像传感器IC的制造方法
公开(公告)号：US08465999B2
公开(公告)日：2013-06-18
申请号：US13409744
申请日：2012-03-01
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L21/00
CPC分类号： H01L27/14601 , H01L27/14692
摘要： In a manufacturing method for an image sensor integrated circuit, a plurality of pixel regions each having a photodiode are arranged on a silicon substrate. A light-transmissive conductive film is formed over the silicon substrate. A protective film is formed on the light-transmissive conductive film while holding a potential of the light-transmissive conductive film at the same potential as that of the silicon substrate.
摘要翻译：在图像传感器集成电路的制造方法中，在硅基板上配置有具有光电二极管的多个像素区域。在硅衬底上形成透光导电膜。在透光导电膜上形成保护膜，同时将透光导电膜的电位保持在与硅衬底相同的电位。

19. 发明授权

US07880240B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07880240B2
公开(公告)日：2011-02-01
申请号：US12070132
申请日：2008-02-15
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/66
CPC分类号： H01L27/0921 , H01L21/823871 , H01L21/823878
摘要： A semiconductor device has a high voltage circuit section disposed on a semiconductor substrate having a first conductivity. The high voltage circuit section has a well region with a second conductivity, a first heavily doped impurity region with the first conductivity and disposed on the well region, a second heavily doped impurity region having a second conductivity and disposed on the semiconductor substrate, a trench isolation region disposed between the first and second heavily doped impurity regions, and an interconnect disposed over the trench isolation region. First and second electrodes are disposed above the trench isolation region, below the interconnect, and on opposite sides of a junction between the well region and the semiconductor substrate. The first electrode is disposed above the semiconductor substrate, and the second electrode is disposed above the well region. The first and second electrodes prevent parasitic formation of an inverse layer on a surface of the semiconductor substrate due to a potential of the interconnect.
摘要翻译：半导体器件具有设置在具有第一导电性的半导体衬底上的高压电路部分。高电压电路部分具有具有第二导电性的阱区域，具有第一导电性的第一重掺杂杂质区域并且设置在阱区域上，具有第二导电性的第二重掺杂杂质区域并且设置在半导体衬底上，沟槽隔离区域设置在第一和第二重掺杂杂质区域之间，以及设置在沟槽隔离区域上的互连。第一和第二电极设置在沟槽隔离区的上方，互连下方，以及阱区和半导体衬底之间的结的相对侧。第一电极设置在半导体衬底之上，第二电极设置在阱区上方。第一和第二电极由于互连的电位而防止半导体衬底的表面上的反层的寄生形成。

20. 发明申请

US20080197425A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080197425A1
公开(公告)日：2008-08-21
申请号：US12070132
申请日：2008-02-15
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/78
CPC分类号： H01L27/0921 , H01L21/823871 , H01L21/823878
摘要： A semiconductor device has a trench isolation structure and a high voltage circuit section including at least one well region, a MOS transistor, and an interconnect for electrically connecting elements. An electrode for preventing inversion layer formation is formed in a region above the trench isolation region provided near an end portion of the well region and below the interconnect for preventing parasitic formation of an inversion layer on a surface of the semiconductor substrate due to the potential of the interconnect, and fixed at the same potential as that of the semiconductor substrate therebelow. Further, a guard ring region formed of a heavily doped impurity region of the same conductivity type as the semiconductor substrate is provided below the electrode for preventing inversion layer formation and is fixed at the same potential as that of the semiconductor substrate to capture carriers to prevent latch-up.
摘要翻译：半导体器件具有沟槽隔离结构和包括至少一个阱区，MOS晶体管和用于电连接元件的互连的高压电路部分。用于防止反型层形成的电极形成在设置在阱区的端部附近和沟槽下方的沟槽隔离区以上的区域中，以防止半导体衬底的表面上的反型层的寄生形成，并且固定在与其下的半导体衬底相同的电位。此外，由与半导体衬底相同的导电类型的重掺杂杂质区形成的保护环区域设置在用于防止反型层形成的电极的下面，并且固定在与半导体衬底相同的电位以捕获载体以防止闭锁。

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