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11. 发明申请

US20110075782A1 STREAM CLOCK RECOVERY IN HIGH DEFINITION MULTIMEDIA DIGITAL SYSTEM 有权
标题翻译：高定义多媒体数字系统中的时钟恢复
公开(公告)号：US20110075782A1
公开(公告)日：2011-03-31
申请号：US12571210
申请日：2009-09-30
申请人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
发明人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
IPC分类号： H04L7/00
CPC分类号： H04J3/062 , G09G5/008 , H03L7/193 , H03L7/1978 , H04N21/4122 , H04N21/4307
摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.
摘要翻译：本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。分数N PLL提供灵活的源流时钟恢复。当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

12. 发明申请

US20100046557A1 MANAGING TRANSMIT JITTER FOR MULTI-FORMAT DIGITAL AUDIO TRANSMISSION 有权
标题翻译：管理用于多格式数字音频传输的发送器
公开(公告)号：US20100046557A1
公开(公告)日：2010-02-25
申请号：US12194080
申请日：2008-08-19
申请人： ZHIYONG GUAN , Xiaoqian Zhang , Qi Li
发明人： ZHIYONG GUAN , Xiaoqian Zhang , Qi Li
IPC分类号： H04L29/02
CPC分类号： H04N7/083 , G09G5/006 , G09G2370/12
摘要： A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.
摘要翻译：提供了一种通过数字接口传输音频数据的方法。该方法包括接收被组织为多个音频样本的音频数据。多个音频样本中的至少一个可以被放置在数据分组中。如果数据分组已满或响应于接收分组发送事件的有效传输间隔，则可以在有效传输间隔期间传输数据分组。

13. 发明授权

US07573896B2 Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device 有权
标题翻译：用于通用接口，分组切换，超量预订，队列级联和系统分组接口设备的逻辑标识优先级的方法和装置
公开(公告)号：US07573896B2
公开(公告)日：2009-08-11
申请号：US11250873
申请日：2005-10-14
申请人： Sibing Wang , Xiaoqian Zhang , Zhonghai Gan , Shubing Zhai
发明人： Sibing Wang , Xiaoqian Zhang , Zhonghai Gan , Shubing Zhai
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/12 , H04L47/17 , H04L47/26 , H04L47/29 , H04L47/30 , H04L49/352
摘要： A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.
摘要翻译：已经公开了用于系统分组接口设备的通用接口，分组切换，超量预定，队列级联和逻辑标识优先级的方法和装置。

14. 发明申请

US20060083185A1 Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device 有权
公开(公告)号：US20060083185A1
公开(公告)日：2006-04-20
申请号：US11250873
申请日：2005-10-14
申请人： Sibing Wang , Xiaoqian Zhang , Zhonghai Gan , Shubing Zhai
发明人： Sibing Wang , Xiaoqian Zhang , Zhonghai Gan , Shubing Zhai
IPC分类号： H04L5/22
CPC分类号： H04L47/10 , H04L47/12 , H04L47/17 , H04L47/26 , H04L47/29 , H04L47/30 , H04L49/352
摘要： A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

15. 发明授权

US08422518B2 Managing transmit jitter for multi-format digital audio transmission 有权
标题翻译：管理多格式数字音频传输的传输抖动
公开(公告)号：US08422518B2
公开(公告)日：2013-04-16
申请号：US12194080
申请日：2008-08-19
申请人： Zhiyong Guan , Xiaoqian Zhang , Qi Li
发明人： Zhiyong Guan , Xiaoqian Zhang , Qi Li
IPC分类号： H04J3/06
CPC分类号： H04N7/083 , G09G5/006 , G09G2370/12
摘要： A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.
摘要翻译：提供了一种通过数字接口传输音频数据的方法。该方法包括接收被组织为多个音频样本的音频数据。多个音频样本中的至少一个可以被放置在数据分组中。如果数据分组已满或响应于接收分组发送事件的有效传输间隔，则可以在有效传输间隔期间传输数据分组。

16. 发明申请

US20110267116A1 METHOD AND CIRCUIT FOR DISPLAYPORT VIDEO CLOCK RECOVERY 有权
标题翻译：显示视频时钟恢复的方法和电路
公开(公告)号：US20110267116A1
公开(公告)日：2011-11-03
申请号：US12675106
申请日：2010-01-19
申请人： Lu Yang , Sibing Wang , Xiaoqian Zhang
发明人： Lu Yang , Sibing Wang , Xiaoqian Zhang
IPC分类号： H03L7/08
CPC分类号： H03L7/0807 , H03L7/16
摘要： A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
摘要翻译：描述了一种用于恢复DisplayPort接收机的视频时钟的方法和电路。本公开包括两个时钟分频器，直接数字合成（DDS），DisplayPort视频系统上的固定乘法器锁相环（PLL）。 DisplayPort接收器链路时钟被划分为较低频率作为DDS的输入，这可以降低DDS电路的性能要求。来自时间戳值的输出间接地控制直接数字合成装置，然后驱动PLL以产生恢复时钟信号。该技术适用于集成电路和现场可编程门阵列系统的实现。

17. 发明授权

US07940662B2 Method and apparatus for forwarding bursty data 有权
标题翻译：用于转发突发数据的方法和装置
公开(公告)号：US07940662B2
公开(公告)日：2011-05-10
申请号：US10861897
申请日：2004-06-04
申请人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
发明人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
IPC分类号： H04L12/26
CPC分类号： H04L29/06 , H04L47/10 , H04L47/22 , H04L47/30 , H04L49/103 , H04L69/324
摘要： Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.
摘要翻译：从突发接口接收的数据以突发为基础接收。一旦接收到脉冲串，它就被存储在处理队列中。接收到完整的脉冲串，处理队列可以容纳数据脉冲串。完整的数据脉冲串被引导到输出端，用于在所述输出端创建完整的数据脉冲串。只要接收端口能够接收输出脉冲串，就调度输出脉冲串。

18. 发明申请

US20090237132A1 Phase-locked loop 有权
标题翻译：锁相环
公开(公告)号：US20090237132A1
公开(公告)日：2009-09-24
申请号：US12077929
申请日：2008-03-20
申请人： Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
发明人： Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
IPC分类号： H03L7/085
CPC分类号： H03L7/18 , H03L7/0891
摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.
摘要翻译：一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。

19. 发明申请

US20060039284A1 Method and apparatus for processing a complete burst of data 审中-公开
标题翻译：用于处理完整数据突发的方法和装置
公开(公告)号：US20060039284A1
公开(公告)日：2006-02-23
申请号：US11102996
申请日：2005-04-11
申请人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
发明人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
IPC分类号： H04J1/16
CPC分类号： H04L49/901 , H04L49/90
摘要： Disclosed are a method and apparatus for processing a complete burst of data by receiving said complete burst of data, storing the complete burst of data in a memory, associating the complete burst of data with a first logical channel and dispatching an egress burst of data according to one or more complete bursts of data stored in a memory and associated with the first logical channel.
摘要翻译：公开了一种用于通过接收所述完整的数据突发来处理完整的数据突发的方法和装置，将完整的数据突发存储在存储器中，将完整的数据突发与第一逻辑信道相关联，并根据到存储在存储器中并与第一逻辑信道相关联的一个或多个完整的数据脉冲串。

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