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11. 发明申请

US20050077628A1 Dual damascene structure and method 有权
公开(公告)号：US20050077628A1
公开(公告)日：2005-04-14
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

12. 发明授权

US07125792B2 Dual damascene structure and method 有权
标题翻译：双镶嵌结构和方法
公开(公告)号：US07125792B2
公开(公告)日：2006-10-24
申请号：US10685055
申请日：2003-10-14
申请人： Kaushik Kumar , Douglas C. La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
发明人： Kaushik Kumar , Douglas C. La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01J37/32862 , H01L21/02046 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136 , H01L21/76811
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.
摘要翻译：一种双镶嵌结构及其制造方法。绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案不同于第一图案。第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。

13. 发明申请

US20060292852A1 BACK END INTERCONNECT WITH A SHAPED INTERFACE 失效
标题翻译：后端互连与形状接口
公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

14. 发明授权

US07091612B2 Dual damascene structure and method 有权
公开(公告)号：US07091612B2
公开(公告)日：2006-08-15
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L23/12 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

15. 发明申请

US20050208742A1 OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING 审中-公开
标题翻译：氧化氮化钛作为双重加工过程中改进的硬质合金
公开(公告)号：US20050208742A1
公开(公告)日：2005-09-22
申请号：US10708648
申请日：2004-03-17
申请人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
发明人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76811 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76834
摘要： A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.
摘要翻译：描述了用于双镶嵌加工的氧化氮化钽（TaO x N N N x S）硬掩模层的制造方法。精细的双镶嵌加工对硬掩模产生了竞争，冲突的要求。尽管临界尺寸控制需要较厚的硬掩模，但由于厚氮化钽（TaN）的不透明度，光学平版印刷对挫败感到沮丧。该技术通过氧化TaN层来解决厚度增加的TaN硬掩模不透明度问题。 TaN硬掩模的氧化将硬掩模的厚度增加到其原始厚度的两到四倍，同时将其透明度提高了十倍以上。这允许与更厚的硬掩模相关联的更好的CD控制，同时促进光学光刻对准。

16. 发明申请

US20050079706A1 Dual damascene structure and method 有权
标题翻译：双镶嵌结构和方法
公开(公告)号：US20050079706A1
公开(公告)日：2005-04-14
申请号：US10685055
申请日：2003-10-14
申请人： Kaushik Kumar , Douglas La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
发明人： Kaushik Kumar , Douglas La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76835 , H01J37/32862 , H01L21/02046 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136 , H01L21/76811
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.
摘要翻译：一种双镶嵌结构及其制造方法。绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案与第一图案不同。第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。

17. 发明申请

US20050067702A1 Plasma surface modification and passivation of organo-silicate glass films for improved hardmask adhesion and optimal RIE processing 审中-公开
标题翻译：有机硅玻璃薄膜的等离子体表面改性和钝化，用于改进硬掩模粘附和最佳的RIE加工
公开(公告)号：US20050067702A1
公开(公告)日：2005-03-31
申请号：US10674646
申请日：2003-09-30
申请人： William America , Timothy Dalton , Kaushik Kumar , Heidi Wickland
发明人： William America , Timothy Dalton , Kaushik Kumar , Heidi Wickland
IPC分类号： H01L21/033 , H01L21/312 , H01L21/768 , H01L21/4763 , H01L23/02 , H01L29/40
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/0332 , H01L21/3122 , H01L21/76802 , H01L21/76826 , H01L21/76829
摘要： Interconnect structure having enhanced adhesion between the various interfaces encompassing an organo-silicate glass (OSG) film, for use in semiconductor devices is provided herein. The novel interconnect structure includes a non-damaged plasma-treated low-k OSG surface to enhance the adhesion of the hardmask material to the OSG surface, and an unique deposition scheme for the hardmasks in order to make the entire structure pliant towards implementing mild processing condition during the reactive ion etch patterning of the dielectric structure in a damascene and dual-damascene scheme. The methods for making a semiconductor device having an enhanced adhesion and micromasks free profiles are also provided.
摘要翻译：本文提供了在包括用于半导体器件的有机硅酸盐玻璃（OSG）膜的各种界面之间具有增强的粘附性的互连结构。新颖的互连结构包括未损坏的等离子体处理的低k OSG表面，以增强硬掩模材料对OSG表面的粘附性，以及用于硬掩模的独特沉积方案，以使整个结构趋于实现温和加工在大马士革和双镶嵌方案中的电介质结构的反应离子蚀刻图案化期间的条件。还提供了制造具有增强的粘合性和微掩模免费型材的半导体器件的方法。

18. 发明申请

US20060094230A1 Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
标题翻译：多层抗扰性方案实现每层专用的蚀刻配方
公开(公告)号：US20060094230A1
公开(公告)日：2006-05-04
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
发明人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

19. 发明申请

US20070048981A1 METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE FROM CARBON DEPLETION BASED DAMAGE 审中-公开
标题翻译：用于保护基于碳沉积的损伤的半导体器件的方法
公开(公告)号：US20070048981A1
公开(公告)日：2007-03-01
申请号：US11162219
申请日：2005-09-01
申请人： Griselda Bonilla , Richard Conti , Timothy Dalton , Nicholas Fuller , Kelly Malone , Satyanarayana Nitta , Shom Ponoth
发明人： Griselda Bonilla , Richard Conti , Timothy Dalton , Nicholas Fuller , Kelly Malone , Satyanarayana Nitta , Shom Ponoth
IPC分类号： H01L21/04
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/76826
摘要： A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.
摘要翻译：用于保护半导体器件免受碳耗竭型损伤的方法包括用碳基材料富集多孔层间电介质材料（ILD）的暴露表面，以及对多孔ILD材料实施基于等离子体的操作。作为基于等离子体的操作的结果，多孔ILD材料的富集减少了碳耗竭的影响。

20. 发明申请

US20060099816A1 System and method for plasma induced modification and improvement of critical dimension uniformity 有权
标题翻译：用于等离子体诱导修饰和改善临界尺寸均匀性的系统和方法
公开(公告)号：US20060099816A1
公开(公告)日：2006-05-11
申请号：US10983345
申请日：2004-11-08
申请人： Timothy Dalton , Ronald Della Guardia , Nicholas Fuller
发明人： Timothy Dalton , Ronald Della Guardia , Nicholas Fuller
IPC分类号： H01L21/461 , H01L47/00 , H01L21/302
CPC分类号： H01L21/31138 , G03F7/40 , G03F7/405 , H01L21/0276 , H01L21/31144
摘要： Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.
摘要翻译：具有OSG或聚合物（90nm及以上的BEOL技术）的新型互连结构，其中采用先进的等离子体处理以减少半导体器件中的后平版印刷光盘不均匀性（“线边缘粗糙度”）。新颖的互连结构具有增强的衬垫和种子保形性，因此能够提供改进的设备性能，功能性和可靠性。

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