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11. 发明授权

US08344445B2 Non-volatile semiconductor memory cell with dual functions 有权
标题翻译：具有双重功能的非易失性半导体存储单元
公开(公告)号：US08344445B2
公开(公告)日：2013-01-01
申请号：US13414734
申请日：2012-03-08
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , G11C17/16 , G11C17/18 , H01L27/11206 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.
摘要翻译：具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。第二扩散区用于接收对应于多次编程功能的第五电压。

12. 发明申请

US20120007161A1 Semiconductor Non-volatile Memory 审中-公开
标题翻译：半导体非易失性存储器
公开(公告)号：US20120007161A1
公开(公告)日：2012-01-12
申请号：US13237976
申请日：2011-09-21
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates.
摘要翻译：在逻辑处理中在非易失性存储单元中形成电荷存储层的方法包括：在衬底的有源区上形成选择栅极，形成与衬底的有源区域部分重叠的长多晶硅栅极，并填充电荷在多晶硅多栅极之间的层间。

13. 发明申请

US20130010518A1 ANTI-FUSE MEMORY ULTILIZING A COUPLING CHANNEL AND OPERATING METHOD THEREOF 有权
标题翻译：防失真存储器可以实现一个耦合通道及其操作方法
公开(公告)号：US20130010518A1
公开(公告)日：2013-01-10
申请号：US13413626
申请日：2012-03-06
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： G11C17/00 , H01L27/088
CPC分类号： H01L27/11206 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.
摘要翻译：提供具有耦合通道的反熔丝存储器。反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。衬底具有隔离结构。掺杂区域设置在衬底中。在掺杂区域和隔离结构之间限定沟道区域。耦合栅极设置在掺杂区域和隔离结构之间的衬底上。耦合栅极与掺杂区域相邻。栅极电介质层设置在耦合栅极和衬底之间。反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。反熔丝栅极和耦合栅极之间具有间隔。反熔丝层设置在反熔丝栅极和衬底之间。

14. 发明申请

US20120223381A1 Non-volatile memory structure and method for manufacturing the same 审中-公开
标题翻译：非易失性存储器结构及其制造方法
公开(公告)号：US20120223381A1
公开(公告)日：2012-09-06
申请号：US13191424
申请日：2011-07-26
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/42344 , H01L29/66833
摘要： A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.
摘要翻译：公开了一种非易失性存储器结构。可以通过使用用于保护有源区的栅极沟道区的掩模的离子注入任选地形成LDD区。两个门彼此分开并且分别设置在有源区域的中间区域的两侧上的隔离结构上。两个门可以各自完全设置在隔离结构上，或者部分地与有效区域的中间区域的侧部重叠。在两个门之间和有源区域上形成电荷俘获层和电介质层，用于存储节点功能。它们可以进一步形成在两个门的所有侧壁上，用作间隔物。通过使用用于保护栅极和电荷俘获层的掩模的离子注入形成源/漏区。

15. 发明申请

US20120163072A1 NON-VOLATILE SEMICONDUCTOR MEMORY CELL WITH DUAL FUNCTIONS 有权
标题翻译：具有双功能的非挥发性半导体存储器单元
公开(公告)号：US20120163072A1
公开(公告)日：2012-06-28
申请号：US13414734
申请日：2012-03-08
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C17/16 , G11C17/18 , H01L27/11206 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.
摘要翻译：具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。第二扩散区用于接收对应于多次编程功能的第五电压。

16. 发明授权

US08390056B2 Non-volatile semiconductor memory device with intrinsic charge trapping layer 有权
标题翻译：具有固有电荷俘获层的非易失性半导体存储器件
公开(公告)号：US08390056B2
公开(公告)日：2013-03-05
申请号：US13253083
申请日：2011-10-05
申请人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
发明人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42344
摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
摘要翻译：非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

17. 发明申请

US20110024823A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER 有权
标题翻译：具有内置电荷捕获层的非易失性半导体存储器件
公开(公告)号：US20110024823A1
公开(公告)日：2011-02-03
申请号：US12633780
申请日：2009-12-08
申请人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
发明人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42344
摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
摘要翻译：非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

18. 发明申请

US20120018794A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER 有权
标题翻译：具有内置电荷捕获层的非易失性半导体存储器件
公开(公告)号：US20120018794A1
公开(公告)日：2012-01-26
申请号：US13253083
申请日：2011-10-05
申请人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
发明人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42344
摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
摘要翻译：非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

19. 发明授权

US08174063B2 Non-volatile semiconductor memory device with intrinsic charge trapping layer 有权
标题翻译：具有固有电荷俘获层的非易失性半导体存储器件
公开(公告)号：US08174063B2
公开(公告)日：2012-05-08
申请号：US12633780
申请日：2009-12-08
申请人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
发明人： Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42344
摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
摘要翻译：非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。第一区域和第二区域被分开足以在其之间形成自对准电荷存储层的距离。

20. 发明授权

US08705289B2 Flash memory apparatus with programming voltage control generators 有权
标题翻译：带编程电压控制发生器的闪存设备
公开(公告)号：US08705289B2
公开(公告)日：2014-04-22
申请号：US13344621
申请日：2012-01-06
申请人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
发明人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/12
摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
摘要翻译：提供一种闪存装置。闪存装置包括多个存储单元和多个编程电压控制发生器。每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

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