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    • 14. 发明授权
    • IGFET Having crystal orientation near (944) to minimize white ribbon
    • IGFET具有接近(944)的晶体取向以最小化白带
    • US4454525A
    • 1984-06-12
    • US215822
    • 1980-12-12
    • Kunihiko WadaMotoo Nakano
    • Kunihiko WadaMotoo Nakano
    • H01L21/205H01L21/762H01L29/04H01L29/78H01L29/786
    • H01L29/78H01L21/76216H01L29/045Y10S438/973
    • Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1,} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.
    • 这里公开的是在单晶硅衬底上形成的IGFET,其中主平面在从{1,0,0}或在(1,0.0)上的晶面{1,1,1}}偏离22度至34度的范围内 形成在所述衬底上的硅外延层。 这里,在使用氮化硅作为掩模的选择氧化工艺中,在掩膜下新形成的氮化硅的产生被抑制,也是降低栅极绝缘膜的击穿电压的主要原因。 此外,根据结晶面取向的各种功能特性根本不受干扰。 因此,本发明可以提供一种IGFET,其将功能特性保持在最佳状态,从而大大提高了栅极绝缘膜的击穿电压故障率。
    • 19. 发明授权
    • Two-tiered dynamic random access memory (DRAM) cell
    • 两层动态随机存取存储器(DRAM)单元
    • US4669062A
    • 1987-05-26
    • US778542
    • 1985-09-20
    • Motoo Nakano
    • Motoo Nakano
    • H01L27/088G11C11/402G11C11/405H01L21/20H01L21/8234H01L21/8242H01L27/00H01L27/06H01L27/10H01L27/108G11C11/34
    • H01L27/0688G11C11/405H01L27/108
    • A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions formed in the substrate and is covered by a first insulating layer and a semiconductor layer. A write select MIS transistor has source and drain regions formed in the semiconducting layer, the first insulating layer having a contact window therein through which the drain regions of the write select and read select MIS transistors are connected. A storage MIS transistor has source, channel and drain regions formed in the substrate, the channel region of the storage MIS transistor comprising the source region of the read select MIS transistor and the drain region of the storage MIS transistor comprising the channel region of the read select MIS transistor, the respective channel regions of the read and storage MIS transistors being formed in a common level in the silicon substrate and directly connected therein between the source region of the storage MIS transistor and the drain region of the read select MIS transistor. The write select MIS transistor further may comprise a separate gate electrode, the gate electrodes of the write and read MIS transistors comprising portions of corresponding, separate conducting lines serving as write select and read select lines, respectively.
    • 动态随机存取存储器(DRAM)单元具有以具有高堆积密度的双层结构排列的三个MIS晶体管。 读选择MIS晶体管具有形成在衬底中的源极,漏极和沟道区,并被第一绝缘层和半导体层覆盖。 写入选择MIS晶体管具有形成在半导体层中的源极和漏极区域,第一绝缘层具有接触窗口,通过该接触窗口连接写入选择和读取选择MIS晶体管的漏极区域。 存储MIS晶体管具有形成在衬底中的源极,沟道和漏极区,存储MIS晶体管的沟道区包括读选择MIS晶体管的源极区和存储MIS晶体管的漏极区,包括读取的沟道区 选择MIS晶体管,读取和存储MIS晶体管的各个沟道区域形成在硅衬底中的公共电平并且直接连接在存储MIS晶体管的源极区域和读选择MIS晶体管的漏极区域之间。 写选择MIS晶体管还可以包括单独的栅电极,写和读MIS晶体管晶体管的栅电极分别包括用作写选择和读选择线的相应的单独导电线的部分。