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11. 发明申请

US20100265011A1 CIRCUIT STRUCTURE AND DESIGN STRUCTURE FOR AN OPTIONALLY SWITCHABLE ON-CHIP SLOW WAVE TRANSMISSION LINE BAND-STOP FILTER AND A METHOD OF MANUFACTURE 有权
标题翻译：用于可选择的可切换的片上慢波传输线连接滤波器的电路结构和设计结构及其制造方法
公开(公告)号：US20100265011A1
公开(公告)日：2010-10-21
申请号：US12424110
申请日：2009-04-15
申请人： Hanyi Ding , Kwan H. Lam , Guoan Wang , Wayne H. Woods, JR.
发明人： Hanyi Ding , Kwan H. Lam , Guoan Wang , Wayne H. Woods, JR.
IPC分类号： H01P3/08 , H05K3/10 , G06F17/50
CPC分类号： H01P1/203 , Y10T29/49155
摘要： The present invention generally relates to a circuit structure, design structure and method of manufacturing a circuit, and more specifically to a circuit structure and design structure for an on-chip slow wave transmission line band-stop filter and a method of manufacture. A structure includes an on-chip transmission line stub comprising a conditionally floating structure structured to provide increased capacitance to the on-chip transmission line stub when the conditionally floating structure is connected to ground.
摘要翻译：本发明一般涉及一种电路结构，电路制造的设计结构和方法，更具体地涉及用于片上慢波传输线带阻滤波器的电路结构和设计结构以及制造方法。一种结构包括片上传输线短截线，其包括有条件浮动结构，其被构造为当有条件浮动结构连接到地时为片上传输线短截线提供增加的电容。

12. 发明授权

US08643191B2 On-chip radial cavity power divider/combiner 有权
标题翻译：片上径向腔功率分配器/组合器
公开(公告)号：US08643191B2
公开(公告)日：2014-02-04
申请号：US13358792
申请日：2012-01-26
申请人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/481 , H01L23/66 , H01L2224/16225 , H01L2924/1305 , H01L2924/15311 , H01L2924/00
摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.
摘要翻译：公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

13. 发明申请

US20130193584A1 ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER 有权
标题翻译：片上径向辐射功率分配器/组合器
公开(公告)号：US20130193584A1
公开(公告)日：2013-08-01
申请号：US13358792
申请日：2012-01-26
申请人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, JR.
发明人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, JR.
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L23/66 , H01L2224/16225 , H01L2924/1305 , H01L2924/15311 , H01L2924/00
摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.
摘要翻译：公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

14. 发明授权

US08405453B2 Millimeter-wave on-chip switch employing frequency-dependent inductance for cancellation of off-state capacitance 有权
标题翻译：使用频率相关电感的毫米波片上开关来消除关态电容
公开(公告)号：US08405453B2
公开(公告)日：2013-03-26
申请号：US12839777
申请日：2010-07-20
申请人： Wayne H. Woods, Jr. , Guoan Wang , Hanyi Ding
发明人： Wayne H. Woods, Jr. , Guoan Wang , Hanyi Ding
IPC分类号： H03K5/00 , H01L27/24
CPC分类号： H01P1/127 , H01F17/0006 , H01L23/5223 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L27/0629 , H01L28/10 , H01L2223/6627 , H01L2924/0002 , H03K17/145 , H01L2924/00
摘要： A semiconductor switching device includes a field effect transistor and an inductor structure that provides a frequency dependent inductance in a parallel connection. During the off-state of the semiconductor switching device, the frequency dependent impedance component due to the off-state parasitic capacitance of the switching device is cancelled by the frequency dependent inductance component of the inductor structure, which provides a non-linear impedance as a function of frequency. The inductor structure provides less inductance at a higher operating frequency than at a lower operating frequency to provide more effective cancellation of two impedance components of the parasitic capacitance and the inductance. Thus, the semiconductor switching device can provide low parasitic coupling at multiple operating frequencies. The operating frequencies of the semiconductor switching device can be at gigahertz ranges for millimeter wave applications.
摘要翻译：半导体开关器件包括场效应晶体管和在并联连接中提供频率相关电感的电感器结构。在半导体开关器件的截止状态期间，由开关器件的截止状态寄生电容引起的与频率相关的阻抗分量被电感器结构的频率相关的电感分量抵消，该电感器结构提供非线性阻抗作为频率功能电感器结构在较高工作频率下提供比在较低工作频率下更小的电感，以提供更有效地消除寄生电容和电感的两个阻抗分量。因此，半导体开关器件可以在多个工作频率下提供低的寄生耦合。对于毫米波应用，半导体开关器件的工作频率可以是千兆赫兹范围。

15. 发明授权

US08188808B2 Compact on-chip branchline coupler using slow wave transmission line 有权
标题翻译：使用慢波传输线的紧凑型片上分支线耦合器
公开(公告)号：US08188808B2
公开(公告)日：2012-05-29
申请号：US12542958
申请日：2009-08-18
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P5/18 , H01P9/00
CPC分类号： H01P3/082 , H01L27/0617 , H01L27/0629 , H01P5/227
摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.
摘要翻译：使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。高阻抗和低阻抗是相对的。高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

16. 发明授权

US07772124B2 Method of manufacturing a through-silicon-via on-chip passive MMW bandpass filter 有权
标题翻译：通过硅片通过片上无源MMW带通滤波器的制造方法
公开(公告)号：US07772124B2
公开(公告)日：2010-08-10
申请号：US12140439
申请日：2008-06-17
申请人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, Jr. , Jiansheng Xu
发明人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, Jr. , Jiansheng Xu
IPC分类号： H01L21/311
CPC分类号： H01L23/64 , H01L23/481 , H01L28/10 , H01L28/40 , H01L2223/6616 , H01L2924/0002 , H01L2924/19011 , H01L2924/19104 , H01L2924/00
摘要： A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.
摘要翻译：通过带通滤波器形成通硅的方法包括形成包括硅层的衬底并在硅层的底侧提供金属层。另外，该方法包括在硅层的顶侧设置电介质层，并且在电介质层的表面上通过带通滤波器形成通硅的顶侧互连。此外，该方法包括在电介质层中形成与顶侧互连接触的多个触点，并分别通过衬底形成多个穿硅通孔并与多个触点和金属层接触。

17. 发明申请

US20090311841A1 Method of Manufacturing a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter 有权
标题翻译：通过硅片通过片上无源MMW带通滤波器制造方法
公开(公告)号：US20090311841A1
公开(公告)日：2009-12-17
申请号：US12140439
申请日：2008-06-17
申请人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, JR. , Jiansheng Xu
发明人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, JR. , Jiansheng Xu
IPC分类号： H01L21/02 , H01L21/4763
CPC分类号： H01L23/64 , H01L23/481 , H01L28/10 , H01L28/40 , H01L2223/6616 , H01L2924/0002 , H01L2924/19011 , H01L2924/19104 , H01L2924/00
摘要： A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.
摘要翻译：通过带通滤波器形成通硅的方法包括形成包括硅层的衬底并在硅层的底侧提供金属层。另外，该方法包括在硅层的顶侧设置电介质层，并且在电介质层的表面上通过带通滤波器形成通硅的顶侧互连。此外，该方法包括在电介质层中形成与顶侧互连接触的多个触点，并分别通过衬底形成多个穿硅通孔并与多个触点和金属层接触。

18. 发明申请

US20090309675A1 Structure for a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter 有权
标题翻译：通过硅片通过片上无源MMW带通滤波器的结构
公开(公告)号：US20090309675A1
公开(公告)日：2009-12-17
申请号：US12140364
申请日：2008-06-17
申请人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, JR. , Jiansheng Xu
发明人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, JR. , Jiansheng Xu
IPC分类号： H03H7/00
CPC分类号： H01P1/20363
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括具有硅层的基板。此外，设计结构包括在硅层的底侧上的金属层和在硅层的顶侧上的介电层。此外，该设计结构包括在电介质层的表面上的通过硅通孔带通滤波器的顶侧互连以及与顶侧互连件接触的介电层中的多个触点。此外，设计结构包括分别通过基板并与多个触点和金属层接触的多个穿硅通孔。

19. 发明授权

US08413098B2 T-connections, methodology for designing T-connections, and compact modeling of T-connections 失效
标题翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模
公开(公告)号：US08413098B2
公开(公告)日：2013-04-02
申请号：US12431887
申请日：2009-04-29
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , G06F17/5036 , G06F17/5063 , G06F17/5072 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.
摘要翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分交界处并且其中T形结和台阶结的顶表面是共面的。

20. 发明授权

US08766748B2 Microstrip line structures with alternating wide and narrow portions having different thicknesses relative to ground, method of manufacture and design structures 有权
标题翻译：具有相对于地面具有不同厚度的交替宽和窄部分的微带线结构，制造方法和设计结构
公开(公告)号：US08766748B2
公开(公告)日：2014-07-01
申请号：US12960009
申请日：2010-12-03
申请人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P3/08 , H01P9/00
CPC分类号： H01P3/081 , H01P3/003 , H01P9/00
摘要： On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.
摘要翻译：本文提供片上高性能慢波微带线结构，集成电路的制造方法和设计结构。该结构包括设置在与至少一个地面不同的平面中的至少一个地面和信号层。信号层具有至少一个交替宽的部分和具有交替厚度的窄部分，使得宽部分的高度不同于窄部分相对于至少一个地面的高度。

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