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1. 发明授权

US08766748B2 Microstrip line structures with alternating wide and narrow portions having different thicknesses relative to ground, method of manufacture and design structures 有权
标题翻译：具有相对于地面具有不同厚度的交替宽和窄部分的微带线结构，制造方法和设计结构
公开(公告)号：US08766748B2
公开(公告)日：2014-07-01
申请号：US12960009
申请日：2010-12-03
申请人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P3/08 , H01P9/00
CPC分类号： H01P3/081 , H01P3/003 , H01P9/00
摘要： On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.
摘要翻译：本文提供片上高性能慢波微带线结构，集成电路的制造方法和设计结构。该结构包括设置在与至少一个地面不同的平面中的至少一个地面和信号层。信号层具有至少一个交替宽的部分和具有交替厚度的窄部分，使得宽部分的高度不同于窄部分相对于至少一个地面的高度。

2. 发明授权

US08963657B2 On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure 有权
标题翻译：通过共面波导结构的片上慢波通硅，制造方法和设计结构
公开(公告)号：US08963657B2
公开(公告)日：2015-02-24
申请号：US13156935
申请日：2011-06-09
申请人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P3/08 , G06F17/50 , H01L21/768 , H01L23/48 , H01P3/00
CPC分类号： H01L23/481 , H01L2924/0002 , H01P3/003 , H01L2924/00
摘要： On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.
摘要翻译：本文提供具有贯穿硅通孔结构的片上，高性能，慢波共面波导，其制造方法和集成电路的设计结构。该方法包括在衬底中形成至少一个接地平面层，并在与该至少一个接地相同的平面层中在衬底中形成信号层。该方法还包括在至少一个接地层与信号层之间形成至少一个填充有金属的硅，

3. 发明申请

US20110043299A1 Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line 有权
标题翻译：使用慢波传输线的紧凑型片上分支线耦合器
公开(公告)号：US20110043299A1
公开(公告)日：2011-02-24
申请号：US12542958
申请日：2009-08-18
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, JR.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, JR.
IPC分类号： H01P5/18 , H01P1/18
CPC分类号： H01P3/082 , H01L27/0617 , H01L27/0629 , H01P5/227
摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.
摘要翻译：使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。高阻抗和低阻抗是相对的。高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

4. 发明授权

US08760245B2 Coplanar waveguide structures with alternating wide and narrow portions having different thicknesses, method of manufacture and design structure 失效
标题翻译：具有不同厚度的交替宽窄部分的共面波导结构，制造方法和设计结构
公开(公告)号：US08760245B2
公开(公告)日：2014-06-24
申请号：US12959997
申请日：2010-12-03
申请人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P3/08 , H01P9/00
CPC分类号： H01P3/081 , H01P3/003 , H01P9/00
摘要： On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness. The wide portion extends toward the at least one ground.
摘要翻译：本文提供片上高性能慢波共面波导结构，集成电路的制造方法和设计结构。该结构包括设置在与至少一个地面相同的平面中的至少一个接地和信号层。信号层具有至少一个交替宽的部分和具有交替厚度的窄部分。宽部分朝向至少一个地面延伸。

5. 发明授权

US08188808B2 Compact on-chip branchline coupler using slow wave transmission line 有权
标题翻译：使用慢波传输线的紧凑型片上分支线耦合器
公开(公告)号：US08188808B2
公开(公告)日：2012-05-29
申请号：US12542958
申请日：2009-08-18
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P5/18 , H01P9/00
CPC分类号： H01P3/082 , H01L27/0617 , H01L27/0629 , H01P5/227
摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.
摘要翻译：使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。高阻抗和低阻抗是相对的。高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

6. 发明授权

US07487473B2 Enabling netlist for modeling of technology dependent BEOL process variation 失效
标题翻译：启用基于技术的BEOL过程变化建模网络表
公开(公告)号：US07487473B2
公开(公告)日：2009-02-03
申请号：US11531023
申请日：2006-09-12
申请人： Essam Mina , William Piper , Wayne H. Woods, Jr.
发明人： Essam Mina , William Piper , Wayne H. Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.
摘要翻译：公开了一种方法，系统和程序产品，其实现了用于对技术依赖的后端（BEOL）过程变化的建模的集成电路（IC）设计的网表。在一个实施例中，该方法包括获得电气元件的网表（即，BEOL寄生电阻和/或电容），所述网表包括电元件的估计电值和至少一个电气元件的几何数据; 基于使用缩放方法的几何数据确定所选择的电气元件的电气值的变化; 并将模型呼叫放置在网表中，模型呼叫实现所选择的电气元件的电气值的变化。经修订的网表可用于对IC设计进行建模，并包括电气值的缩放，而不必生成多个网表。

7. 发明授权

US07490304B2 Determining geometrical configuration of interconnect structure 失效
标题翻译：确定互连结构的几何结构
公开(公告)号：US07490304B2
公开(公告)日：2009-02-10
申请号：US11426053
申请日：2006-06-23
申请人： Essam Mina , William Piper , Wayne H. Woods, Jr.
发明人： Essam Mina , William Piper , Wayne H. Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring a capacitance value and a resistance value from the interconnect structure of the test structure; and determining the geometrical configuration of the interconnect structure by comparing the capacitance value and the resistance value to the simulation data.
摘要翻译：公开了用于确定测试结构的互连结构的几何结构而不进行横截面或光学测量的方法。在一个实施例中，该方法包括获得关于具有不同几何构造的多个互连结构的电容数据，电阻数据和几何配置数据相关联的模拟数据; 从测试结构的互连结构测量电容值和电阻值; 以及通过将电容值和电阻值与仿真数据进行比较来确定互连结构的几何结构。

8. 发明申请

US20120193121A1 HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE 有权
标题翻译：高性能片上垂直同轴电缆，制造方法和设计结构
公开(公告)号：US20120193121A1
公开(公告)日：2012-08-02
申请号：US13018963
申请日：2011-02-01
申请人： Essam Mina , Guoan Wang , Wayne Harvey Woods, JR.
发明人： Essam Mina , Guoan Wang , Wayne Harvey Woods, JR.
IPC分类号： H01B9/02 , H01B13/016 , G06F17/50
CPC分类号： H01L21/768 , G06F17/505 , H01L23/49827 , H01L2924/0002 , Y10T29/49123 , H01L2924/00
摘要： A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.
摘要翻译：提供了一种高性能的片上垂直同轴电缆结构，其制造方法和设计结构。同轴电缆结构包括同轴地围绕内导体的内导体和绝缘材料。该结构还包括围绕绝缘材料的外导体。内导体和外导体都包括形成在不同布线层上的多个金属层，并且通过导体在不同布线层之间互连。同轴电缆结构形成在半导体衬底的表面上并且与表面基本上垂直对齐。

9. 发明授权

US08413098B2 T-connections, methodology for designing T-connections, and compact modeling of T-connections 失效
标题翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模
公开(公告)号：US08413098B2
公开(公告)日：2013-04-02
申请号：US12431887
申请日：2009-04-29
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , G06F17/5036 , G06F17/5063 , G06F17/5072 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.
摘要翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分交界处并且其中T形结和台阶结的顶表面是共面的。

10. 发明申请

US20100156559A1 MILLIMETER WAVE TRANSMISSION LINE FOR SLOW PHASE VELOCITY 有权
标题翻译：用于慢速相速度的MILLIMETER WAVE TRANSMISSION LINE
公开(公告)号：US20100156559A1
公开(公告)日：2010-06-24
申请号：US12342271
申请日：2008-12-23
申请人： Guoan Wang , Essam Mina
发明人： Guoan Wang , Essam Mina
IPC分类号： H01P1/18 , H01P3/08 , G06F19/00
CPC分类号： H01P3/026 , H01P1/184 , H01P3/088
摘要： A grounding plate and a transmission line are provided in a stack of dielectric material layers. First transmission line portions having a first width are alternately interlaced with second transmission line portions having a second width in the transmission line. The second width is greater than the first width so that inductance of the transmission line is increased relative to a transmission line having a fixed width. Metal fins may be provided between the grounding plate and the transmission line in the stack of the dielectric material layers. The metal fins may be grounded to the grounding plate to increase capacitance between the transmission line and the grounding plate. The increase in the inductance and the capacitance per unit length between the transmission line and the grounding plate is advantageously employed to provide a reduced phase velocity for electromagnetic signal transmitted through the transmission line. A design structure for the transmission line structure is provided.
摘要翻译：接地板和传输线设置在电介质材料层的堆叠中。具有第一宽度的第一传输线部分与传输线中具有第二宽度的第二传输线部分交替交织。第二宽度大于第一宽度，使得传输线的电感相对于具有固定宽度的传输线增加。可以在接地板和介电材料层的叠层中的传输线之间设置金属翅片。金属翅片可以接地到接地板，以增加传输线和接地板之间的电容。传输线和接地板之间的电感和每单位长度的电容的增加有利地用于为通过传输线传输的电磁信号提供降低的相位速度。提供了传输线结构的设计结构。

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