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11. 发明授权

US08416599B2 Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same 有权
标题翻译：具有沟槽隔离区域的金属氧化物半导体（MOS）场效应晶体管及其制造方法
公开(公告)号：US08416599B2
公开(公告)日：2013-04-09
申请号：US12498652
申请日：2009-07-07
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： G11C11/00
CPC分类号： H01L21/823481 , H01L29/78
摘要： A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.
摘要翻译：在金属氧化物半导体（MOS）场效应晶体管中，可以防止在沟槽隔离区域和有源区域的边界上产生的漏电流，并提供其制造方法。晶体管包括设置在半导体衬底的预定部分中以限定有源区的沟槽隔离区。源极区域和漏极区域在有源区域内彼此间隔开，沟道区域设置在源极区域和漏极区域之间。栅电极跨越源极区域和漏极区域之间的沟道区域，栅极绝缘层设置在栅电极和沟道区域之间。在沟槽隔离区域和有源区域的边界周围的栅电极的下表面上设置比栅绝缘层厚的边缘绝缘层。

12. 发明申请

US20100155856A1 Transistor, a transistor arrangement and method thereof 有权
公开(公告)号：US20100155856A1
公开(公告)日：2010-06-24
申请号：US12659107
申请日：2010-02-25
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

13. 发明授权

US07696054B2 Transistor, a transistor arrangement and method thereof 有权
标题翻译：晶体管，晶体管结构及其方法
公开(公告)号：US07696054B2
公开(公告)日：2010-04-13
申请号：US11802004
申请日：2007-05-18
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
摘要翻译：提供一种晶体管，晶体管结构及其方法。示例性方法可以包括确定晶体管的栅极宽度是否已被调整; 以及如果所述确定步骤确定所述晶体管的栅极宽度，则基于所述调整的栅极宽度来调整所述晶体管的高浓度杂质掺杂区域和所述晶体管的器件隔离层之间的距离。示例性晶体管可以包括限定第一有源区的第一器件隔离层，具有第一栅极宽度并与第一有源区交叉的第一栅极线，首先在第一有源区中形成的第一低浓度杂质掺杂区和第一栅极线的第二面和形成在低浓度杂质掺杂区域中的第一较高浓度杂质掺杂区，并且不与栅极线和器件隔离层接触。

14. 发明授权

US06448130B1 Method of selectively forming silicide film of merged DRAM and Logic 失效
标题翻译：选择性地形成合并DRAM和逻辑的硅化物膜的方法
公开(公告)号：US06448130B1
公开(公告)日：2002-09-10
申请号：US09941345
申请日：2001-08-29
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L218247
CPC分类号： H01L27/10894 , H01L21/76832 , H01L21/76837 , H01L21/823814 , H01L21/823835 , H01L27/10873
摘要： Disclosed is a method of selectively forming a silicide film of merged DRAM logic by which active regions of a logic side are entirely changed into a silicidation state without adding a separate photoresist patterning process even though there exist any regions in which the space between gates is somewhat narrower than in a DRAM cell forming region, and an etch stopper film of SiON material that is needed in the formation of deep contacts can be applied to a MDL process having dual gate in mass production.
摘要翻译：公开了一种选择性地形成合并的DRAM逻辑的硅化物膜的方法，即使存在门之间的空间有些区域，逻辑侧的有源区域也完全改变为硅化状态而不添加单独的光刻胶图案化工艺比DRAM单元形成区域窄，并且形成深触点所需的SiON材料的蚀刻停止膜可以应用于具有双栅极的大批量生产的MDL工艺。

15. 发明授权

US07868371B2 Non-volatile memory device and fabrication method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07868371B2
公开(公告)日：2011-01-11
申请号：US12136580
申请日：2008-06-10
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L27/108
CPC分类号： H01L27/11206 , H01L27/112 , H01L29/66825 , H01L29/7881
摘要： In one embodiment, a non-volatile memory device includes an isolation film defining an active region in a semiconductor substrate; a tunnel insulating film located on the active region; a control gate located on the isolation film; an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film; an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate; and a source region and a drain region formed in the active region on both sides of the floating gate.
摘要翻译：在一个实施例中，非易失性存储器件包括限定半导体衬底中的有源区的隔离膜; 位于有源区上的隧道绝缘膜; 位于隔离膜上的控制门; 栅极间电介质膜平行于控制栅并位于控制栅极和隔离膜之间; 由控制栅极和栅极间电介质膜重叠的电极，其中电极在有源区上的隧道绝缘膜上延伸以形成浮栅; 以及形成在浮置栅极两侧的有源区域中的源极区域和漏极区域。

16. 发明授权

US07723203B2 Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same 有权
标题翻译：形成具有封盖层的对准键的方法和使用其制造半导体器件的方法
公开(公告)号：US07723203B2
公开(公告)日：2010-05-25
申请号：US11524318
申请日：2006-09-21
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/0629 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an active region in a chip region of a semiconductor substrate, and forming an alignment key having a step height difference with respect to the surface of the semiconductor substrate in a scribe lane. An at least one formation layer for forming an element may be formed on the substrate, and patterned, to form an element-forming pattern on the semiconductor substrate in the chip region, and a capping layer capping the alignment key on the semiconductor substrate in the scribe lane.
摘要翻译：可以提供一种在半导体器件中形成具有覆盖层的对准键而不需要额外的掩模形成工艺的方法，以及制造使用其的半导体器件的方法。形成对准键的方法可以包括形成限制半导体衬底的芯片区域中的有源区的隔离层，并且在划线中形成相对于半导体衬底的表面具有台阶高度差的对准键。可以在衬底上形成用于形成元件的至少一个形成层，并且被图案化，以在芯片区域中的半导体衬底上形成元件形成图案，并且在半导体衬底上覆盖对准键的封盖层划线

17. 发明授权

US07422939B2 Semiconductor device having one-time programmable ROM and method of fabricating the same 失效
标题翻译：具有一次可编程ROM的半导体器件及其制造方法
公开(公告)号：US07422939B2
公开(公告)日：2008-09-09
申请号：US11448200
申请日：2006-06-07
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/11531 , H01L29/66825
摘要： A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The OTP ROM capacitor has a lower electrode, an upper intermetal dielectric, and an upper electrode which are stacked in the order named. The OTP ROM capacitor is disposed on the MOS transistor, and the floating gate electrode and the lower electrode are connected by a floating gate plug to constitute an electrically insulated conductive structure. The upper intermetal dielectric is made of at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride and may be disposed on an entire surface of the semiconductor substrate. A capacitor formed together with the OTP ROM is disposed at the peripheral circuit region.
摘要翻译：具有设置在包括存储单元区域和外围电路区域的半导体衬底上的一次可编程（OTP）ROM的半导体器件包括MOS晶体管和OTP ROM电容器。 MOS晶体管具有浮置栅电极，并且设置在存储单元区域。 OTP ROM电容器具有按所述顺序堆叠的下电极，上金属间电介质和上电极。 OTP ROM电容器设置在MOS晶体管上，浮栅电极和下电极通过浮栅连接，构成绝缘导电结构。上部金属间电介质由选自氧化硅，氮化硅和氮氧化硅中的至少一种制成，并且可以设置在半导体衬底的整个表面上。与OTP ROM一起形成的电容器设置在外围电路区域。

18. 发明申请

US20070278598A1 Transistor, a transistor arrangement and method thereof 有权
标题翻译：晶体管，晶体管结构及其方法
公开(公告)号：US20070278598A1
公开(公告)日：2007-12-06
申请号：US11802004
申请日：2007-05-18
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
摘要翻译：提供一种晶体管，晶体管结构及其方法。示例性方法可以包括确定晶体管的栅极宽度是否已被调整; 以及如果所述确定步骤确定所述晶体管的栅极宽度，则基于所述调整的栅极宽度来调整所述晶体管的高浓度杂质掺杂区域和所述晶体管的器件隔离层之间的距离。示例性晶体管可以包括限定第一有源区的第一器件隔离层，具有第一栅极宽度并与第一有源区交叉的第一栅极线，首先在第一有源区中形成的第一低浓度杂质掺杂区和第一栅极线的第二面和形成在低浓度杂质掺杂区域中的第一较高浓度杂质掺杂区，并且不与栅极线和器件隔离层接触。

19. 发明申请

US20070072386A1 Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same 有权
标题翻译：形成具有封盖层的对准键的方法和使用其制造半导体器件的方法
公开(公告)号：US20070072386A1
公开(公告)日：2007-03-29
申请号：US11524318
申请日：2006-09-21
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/0629 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an active region in a chip region of a semiconductor substrate, and forming an alignment key having a step height difference with respect to the surface of the semiconductor substrate in a scribe lane. An at least one formation layer for forming an element may be formed on the substrate, and patterned, to form an element-forming pattern on the semiconductor substrate in the chip region, and a capping layer capping the alignment key on the semiconductor substrate in the scribe lane.
摘要翻译：可以提供一种在半导体器件中形成具有覆盖层的对准键而不需要额外的掩模形成工艺的方法，以及制造使用其的半导体器件的方法。形成对准键的方法可以包括形成限制半导体衬底的芯片区域中的有源区的隔离层，并且在划线中形成相对于半导体衬底的表面具有台阶高度差的对准键。可以在衬底上形成用于形成元件的至少一个形成层，并且被图案化，以在芯片区域中的半导体衬底上形成元件形成图案，并且在半导体衬底上覆盖对准键的封盖层划线

20. 发明授权

US07041563B2 Semiconductor device having a shallow trench isolation and method of fabricating the same 有权
公开(公告)号：US07041563B2
公开(公告)日：2006-05-09
申请号：US10795176
申请日：2004-03-05
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28167 , H01L21/28211 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L29/42368 , H01L29/513 , H01L29/7835
摘要： The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

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