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11. 发明申请

US20160372542A9 TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS 审中-公开
公开(公告)号：US20160372542A9
公开(公告)日：2016-12-22
申请号：US14329936
申请日：2014-07-12
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/761 , H01L29/78
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0619 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

12. 发明申请

US20160013267A1 TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS 审中-公开
标题翻译：具有新配置和方法的高压（HV）器件的终止
公开(公告)号：US20160013267A1
公开(公告)日：2016-01-14
申请号：US14329936
申请日：2014-07-12
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/761 , H01L29/78
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0619 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

13. 发明申请

US20150357406A1 MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES 审中-公开
标题翻译：精确对准和自平衡超级设备的制造方法
公开(公告)号：US20150357406A1
公开(公告)日：2015-12-10
申请号：US14298922
申请日：2014-06-08
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/266 , H01L21/324 , H01L29/10
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
摘要翻译：本发明公开了一种在半导体基板上制造半导体功率器件的方法，漂移区由外延层组成。该方法包括：生长第一外延层，然后在外延层顶部形成第一硬掩模层的第一步骤; 第二步骤，施加第一注入掩模以打开多个植入窗口，并施加第二注入掩模以阻挡一些植入窗口，以在第一外延层中相互邻近地注入交替导电类型的多个掺杂区; 以及通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤以形成多个外延层的第三步骤，其中每个外延层被注入交替导电类型的掺杂区域。然后通过在交变导电类型的掺杂剂区域的顶部上的外延层的顶侧上进行器件制造工艺来进行制造工艺，其具有扩散处理，以将交替导电类型的掺杂区域作为掺杂列合并在外延层。

14. 发明授权

US08785306B2 Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
标题翻译：精确对准和自平衡超级结装置的制造方法
公开(公告)号：US08785306B2
公开(公告)日：2014-07-22
申请号：US13200683
申请日：2011-09-27
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
摘要翻译：一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域交替导电类型作为外延层中的掺杂列。

15. 发明申请

US20170125514A9 MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES 审中-公开
公开(公告)号：US20170125514A9
公开(公告)日：2017-05-04
申请号：US14298922
申请日：2014-06-08
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/266 , H01L21/324 , H01L29/10
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

16. 发明授权

US09647059B2 Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
公开(公告)号：US09647059B2
公开(公告)日：2017-05-09
申请号：US14298922
申请日：2014-06-08
申请人： Lingping Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingping Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L21/8238 , H01L29/06 , H01L21/225 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/266
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

17. 发明申请

US20130075855A1 Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
标题翻译：精确对准和自平衡超级结装置的制造方法
公开(公告)号：US20130075855A1
公开(公告)日：2013-03-28
申请号：US13200683
申请日：2011-09-27
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
摘要翻译：一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域交替导电类型作为外延层中的掺杂列。

18. 发明申请

US20110147830A1 METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS 有权
标题翻译：形成自对准电荷平衡功率DMOS的方法
公开(公告)号：US20110147830A1
公开(公告)日：2011-06-23
申请号：US12643837
申请日：2009-12-21
申请人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/165 , H01L29/456 , H01L29/66719 , H01L29/78 , H01L29/7811
摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.
摘要翻译：公开了自对准电荷平衡半导体器件及其形成方法。在第一导电类型的半导体衬底上形成一个或多个平面栅极。在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

19. 发明授权

US08519476B2 Method of forming a self-aligned charge balanced power DMOS 有权
标题翻译：形成自对准电荷平衡功率DMOS的方法
公开(公告)号：US08519476B2
公开(公告)日：2013-08-27
申请号：US12643837
申请日：2009-12-21
申请人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/66
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/165 , H01L29/456 , H01L29/66719 , H01L29/78 , H01L29/7811
摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.
摘要翻译：公开了自对准电荷平衡半导体器件及其形成方法。在第一导电类型的半导体衬底上形成一个或多个平面栅极。在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

20. 发明申请

US20100291744A1 HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
标题翻译：高密度TRENCH MOSFET，具有单面罩预定门和接触孔
公开(公告)号：US20100291744A1
公开(公告)日：2010-11-18
申请号：US12847863
申请日：2010-07-30
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

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