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11. 发明授权

US08421077B2 Replacement gate MOSFET with self-aligned diffusion contact 有权
标题翻译：具有自对准扩散接触的替代栅极MOSFET
公开(公告)号：US08421077B2
公开(公告)日：2013-04-16
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/10
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译：替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

12. 发明申请

US20090309228A1 METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS 有权
标题翻译：形成自对准金属硅化物接触的方法
公开(公告)号：US20090309228A1
公开(公告)日：2009-12-17
申请号：US12539660
申请日：2009-08-12
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L23/532 , H01L21/306
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

13. 发明授权

US06806177B2 Method of making self-aligned borderless contacts 失效
标题翻译：制定自主对边无边界联系的方法
公开(公告)号：US06806177B2
公开(公告)日：2004-10-19
申请号：US10719861
申请日：2003-11-21
申请人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
发明人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.
摘要翻译：一种在半导体器件中形成高密度自对准触点和互连结构的方法。在衬底上形成足够厚以容纳互连和接触结构的电介质层。在电介质层上形成图形化的硬掩模以限定互连和接触结构。用于互连特征的开口首先通过部分蚀刻对硬掩模有选择性的介电层而形成。使用第二掩模（例如抗蚀剂）来限定接触开口，并且通过第二掩模蚀刻电介质层，也可以对硬掩模进行选择，以暴露待接触的扩散区域。图案化的硬掩模用于帮助定义接触开口。然后将导电材料沉积在开口中，这导致自对准的触点和互连。通过首先形成用于互连和接触的开口，可以获得处理步骤的节省。

14. 发明授权

US08685809B2 Semiconductor structures having improved contact resistance 有权
标题翻译：具有改善的接触电阻的半导体结构
公开(公告)号：US08685809B2
公开(公告)日：2014-04-01
申请号：US13454709
申请日：2012-04-24
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

15. 发明授权

US08101518B2 Method and process for forming a self-aligned silicide contact 有权
标题翻译：用于形成自对准硅化物接触的方法和工艺
公开(公告)号：US08101518B2
公开(公告)日：2012-01-24
申请号：US12136885
申请日：2008-06-11
申请人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。在退火步骤A期间，与绝缘材料（例如SiO 2和Si 3 N 4）直接接触的金属不会转化为金属合金硅化物接触。然后进行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

16. 发明申请

US20110298017A1 REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT 有权
标题翻译：具有自对准扩散接触的更换栅极MOSFET
公开(公告)号：US20110298017A1
公开(公告)日：2011-12-08
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译：替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

17. 发明授权

US08039382B2 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US08039382B2
公开(公告)日：2011-10-18
申请号：US12539660
申请日：2009-08-12
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

18. 发明授权

US07618891B2 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US07618891B2
公开(公告)日：2009-11-17
申请号：US11415922
申请日：2006-05-01
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

19. 发明授权

US07544610B2 Method and process for forming a self-aligned silicide contact 有权
标题翻译：用于形成自对准硅化物接触的方法和工艺
公开(公告)号：US07544610B2
公开(公告)日：2009-06-09
申请号：US10935497
申请日：2004-09-07
申请人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/477 , H01L21/441
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。在绝缘材料如SiO 2和Si 3 N 4中直接接触的金属在退火步骤期间不会转化为金属合金硅化物接触。然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

20. 发明申请

US20080274611A1 METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT 有权
标题翻译：形成自对准硅酮接触的方法和工艺
公开(公告)号：US20080274611A1
公开(公告)日：2008-11-06
申请号：US12136885
申请日：2008-06-11
申请人： Cyril Cabral , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触然后执行退火步骤A选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

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