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11. 发明授权

US08842491B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08842491B2
公开(公告)日：2014-09-23
申请号：US13551597
申请日：2012-07-17
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。该系统包括电耦合到多个列电压的列电压开关。列电压开关包括电耦合到双向存取二极管的输出。多个列电压包括至少一个选择列电压和一个取消选择列电压。该系统包括电耦合到多个行电压的行电压开关。行电压开关包括电耦合到双向存取二极管的输出。多个行电压包括至少一个选择行电压和一个取消选择行电压。该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。

12. 发明授权

US08811060B2 Non-volatile memory crosspoint repair 有权
标题翻译：非易失性存储器交叉点修复
公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
申请人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译：一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。还介绍了其他系统和方法。

13. 发明授权

US08755213B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效
标题翻译：需要双极性编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08755213B2
公开(公告)日：2014-06-17
申请号：US13407848
申请日：2012-02-29
申请人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
发明人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译：一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。该系统包括列电压。列电压开关包括列电压和电耦合到双向存取二极管的输出。列电压包括至少一个写一列电压和至少一个写零列电压。该系统还包括行电压开关。行电压开关包括行电压和电耦合到双向存取二极管的输出。行电压包括至少一个写入一行电压和至少一个写入零行电压。该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。该系统包括电耦合到行和列开关的选择线的写入驱动器。

14. 发明申请

US20130044532A1 LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS 有权
标题翻译：具有高电压容量的低温BEO兼容二极管用于大型电子元件阵列
公开(公告)号：US20130044532A1
公开(公告)日：2013-02-21
申请号：US13209569
申请日：2011-08-15
申请人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
发明人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L29/872 , G11C13/003 , G11C2029/5002 , G11C2029/5006 , G11C2213/72 , H01L27/1021 , H01L27/224 , H01L27/2427 , H01L45/141 , H01L45/1616
摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
摘要翻译：夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。

15. 发明授权

US07382647B1 Rectifying element for a crosspoint based memory array architecture 有权
标题翻译：用于基于交叉点的存储器阵列架构的整流元件
公开(公告)号：US07382647B1
公开(公告)日：2008-06-03
申请号：US11679785
申请日：2007-02-27
申请人： Kailash Gopalakrishnan
发明人： Kailash Gopalakrishnan
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/224
摘要： An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.
摘要翻译：描述了一种不对称编程的记忆材料（例如固体电解质材料），用作整流元件，用于驱动交叉点存储器架构中的对称或基本对称的电阻性存储器元件。固体电解质元件（SE）在OFF状态下具有非常高的电阻，并且在ON状态下具有非常低的电阻（因为它是处于ON状态的金属灯丝）。这些属性使其成为接近理想的二极管。在存储元件的电流（在编程/读取/擦除期间）期间，固体电解质材料也编程到低电阻状态。固体电解质材料的最终状态被还原成高电阻状态，同时确保记忆材料的最终状态是期望的。

16. 发明授权

US07920406B2 Increasing effective transistor width in memory arrays with dual bitlines 有权
标题翻译：在双位线存储器阵列中增加有效的晶体管宽度
公开(公告)号：US07920406B2
公开(公告)日：2011-04-05
申请号：US12180586
申请日：2008-07-28
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：一种用于形成存储器结构的方法，包括：形成布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元还包括能够被编程为多个电阻状态的电阻性存储器件每个电阻存储器件在其第一端处耦合到位线之一; 在其第二端配置与每个所述电阻式存储器件串联的整流元件; 配置与每个单独存储器单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及形成公共连接，其被配置为沿着字线方向将两个或更多个组的相邻整流装置短路在一起。

17. 发明申请

US20100248441A1 MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES 有权
标题翻译：多位高密度存储器件和架构以及制造多位高密度存储器件的方法
公开(公告)号：US20100248441A1
公开(公告)日：2010-09-30
申请号：US12794826
申请日：2010-06-07
申请人： Kailash Gopalakrishnan , Rohit Sudhir Shenoy
发明人： Kailash Gopalakrishnan , Rohit Sudhir Shenoy
IPC分类号： H01L21/425 , H01L21/20
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译：一种结构，使用该结构的存储器件以及该结构的制造方法。该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中，每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二共同接触点在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。

18. 发明申请

US20080314738A1 Electrolytic Device Based on a Solution-Processed Electrolyte 审中-公开
标题翻译：基于溶液处理电解质的电解装置
公开(公告)号：US20080314738A1
公开(公告)日：2008-12-25
申请号：US11765142
申请日：2007-06-19
申请人： Kailash Gopalakrishnan , David B. Mitzi , Rohit S. Shenoy
发明人： Kailash Gopalakrishnan , David B. Mitzi , Rohit S. Shenoy
IPC分类号： C25B9/06 , B05D5/12 , H01L21/64
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译：本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。无定形硫族化物固体活性电解质层位于第一和第二金属层之间。无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的，将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。本公开还涉及制造固体电解质器件的方法。

19. 发明申请

US20080225578A1 STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES 审中-公开
标题翻译：增加有效半导体存储器阵列中有效半导体结构的结构
公开(公告)号：US20080225578A1
公开(公告)日：2008-09-18
申请号：US12055907
申请日：2008-03-26
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：存储器结构包括：布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元进一步包括能够被编程为多个电阻状态的电阻性存储器件，每个电阻状态在其第一端耦合到位线中的一个的存储器件; 整流元件，其每个电阻存储器件在其第二端处串联; 与每个单独的存储单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及公共连接，其被配置为沿着字线方向以两个或更多个组的形式将相邻整流装置短路。

20. 发明申请

US20080068065A1 ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE 失效
公开(公告)号：US20080068065A1
公开(公告)日：2008-03-20
申请号：US11926031
申请日：2007-10-28
申请人： Hemantha Wickramasinghe , Kailash Gopalakrishnan
发明人： Hemantha Wickramasinghe , Kailash Gopalakrishnan
IPC分类号： H03K17/00
CPC分类号： H01L27/1203 , G11C16/08 , H01L21/84 , H01L27/115 , Y10S977/936 , Y10S977/938 , Y10S977/958
摘要： An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

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