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11. 发明申请

US20080248632A1 Methods of Fabricating Multi-Bit Phase-Change Memory Devices and Devices Formed Thereby 有权
标题翻译：制造由此形成的多位相变存储器件和器件的方法
公开(公告)号：US20080248632A1
公开(公告)日：2008-10-09
申请号：US12062905
申请日：2008-04-04
申请人： Sun Pil Youn , Jin-Tae Kang , Young-Jae Joo , Hyeong-Jun Kim , Jae-Min Shin
发明人： Sun Pil Youn , Jin-Tae Kang , Young-Jae Joo , Hyeong-Jun Kim , Jae-Min Shin
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , G11C11/5678 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1658 , H01L45/1683
摘要： Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data when serially programmed using at least four serial program currents. Each of the plurality of phase-changeable material regions has different electrical resistance characteristics when programmed.
摘要翻译：形成集成电路器件的方法包括在衬底上形成至少一个非易失性存储单元。该存储单元包括多个相互电耦合的相变材料区域。该多个可相位改变的材料区域被共同配置为在使用至少四个串行程序电流进行串行编程时支持至少2位的数据。当编程时，多个相变材料区域中的每一个具有不同的电阻特性。

12. 发明授权

US08203682B2 Display substrate, method of manufacturing the same and display panel having the display substrate 有权
标题翻译：显示基板，其制造方法以及具有显示基板的显示面板
公开(公告)号：US08203682B2
公开(公告)日：2012-06-19
申请号：US12181678
申请日：2008-07-29
申请人： Hong-Woo Lee , Jong-Oh Kim , Sung-Man Kim , Sun-Kyu Joo , Bong-Jun Lee , Jae-Min Shin
发明人： Hong-Woo Lee , Jong-Oh Kim , Sung-Man Kim , Sun-Kyu Joo , Bong-Jun Lee , Jae-Min Shin
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213
摘要： A display substrate includes a first switching element, a second switching element, a first pixel electrode, a second pixel electrode, a main storage electrode and a sub-storage electrode. The first switching element is connected to a data line and a first gate line. The second switching element is connected to the data line and a second gate line adjacent to the first gate line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The main storage electrode is disposed in an area between the first pixel electrode and the second electrode to overlap with first ends of the first and second pixel electrodes. The sub-storage electrode is spaced apart from the first and second gate lines.
摘要翻译：显示基板包括第一开关元件，第二开关元件，第一像素电极，第二像素电极，主存储电极和副存储电极。第一开关元件连接到数据线和第一栅极线。第二开关元件连接到数据线和与第一栅极线相邻的第二栅极线。第一像素电极电连接到第一开关元件。第二像素电极电连接到第二开关元件。主存储电极设置在第一像素电极和第二电极之间的区域中，以与第一和第二像素电极的第一端重叠。副存储电极与第一和第二栅极线间隔开。

13. 发明授权

US08203135B2 Semiconductor device including uniform contact plugs and a method of manufacturing the same 有权
标题翻译：包括均匀接触塞的半导体器件及其制造方法
公开(公告)号：US08203135B2
公开(公告)日：2012-06-19
申请号：US12697620
申请日：2010-02-01
申请人： Kyu-Rie Sim , Jung-Hoon Park , Yoon-Jong Song , Jae-Min Shin , Shin-Hee Han
发明人： Kyu-Rie Sim , Jung-Hoon Park , Yoon-Jong Song , Jae-Min Shin , Shin-Hee Han
IPC分类号： H01L29/41
CPC分类号： H01L27/24 , H01L27/222
摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.
摘要翻译：提供半导体器件，半导体模块，电子设备及其制造和制造方法。半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案，形成在存储图案上的多个上电极和形成在上电极上的多个上互连。下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

14. 发明授权

US07778079B2 Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices 有权
标题翻译：具有后编程操作电阻漂移饱和的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法
公开(公告)号：US07778079B2
公开(公告)日：2010-08-17
申请号：US12079892
申请日：2008-03-28
申请人： Chang-Wook Jeong , Dae-Hwan Kang , Hyeong-Jun Kim , Jae-Min Shin , Seung-Pil Ko
发明人： Chang-Wook Jeong , Dae-Hwan Kang , Hyeong-Jun Kim , Jae-Min Shin , Seung-Pil Ko
IPC分类号： G11C16/06
CPC分类号： G11C11/5678 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/0078
摘要： In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.
摘要翻译：在存储器件和其编程方法中，存储器件包括：多个存储器单元，每个存储器单元包括电阻可变材料，该电阻可变材料具有响应于在一个应用编程电流中确定的初始电阻编程操作; 以及修改电路，其在存储单元的编程操作之后修改存储单元的电阻，以通过在饱和运算中施加饱和电流来将存储单元的电阻从初始电阻改变为第二电阻。每个存储单元连接到存储器件的导线，该导线用于施加编程电流以对编程操作中对应的存储单元的电阻进行编程，用于将饱和电流施加到相应的存储单元中饱和操作，并且用于在随后的读取操作中应用读取电流来读取相应存储器单元的电阻。

15. 发明授权

US07704788B2 Methods of fabricating multi-bit phase-change memory devices and devices formed thereby 有权
标题翻译：制造多位相变存储器件和由此形成的器件的方法
公开(公告)号：US07704788B2
公开(公告)日：2010-04-27
申请号：US12062905
申请日：2008-04-04
申请人： Sun-Pil Youn , Jin-Tae Kang , Young-Jae Joo , Hyeong-Jun Kim , Jae-Min Shin
发明人： Sun-Pil Youn , Jin-Tae Kang , Young-Jae Joo , Hyeong-Jun Kim , Jae-Min Shin
IPC分类号： H01L21/06 , H01L21/00
CPC分类号： H01L45/06 , G11C11/5678 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1658 , H01L45/1683
摘要： Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data when serially programmed using at least four serial program currents. Each of the plurality of phase-changeable material regions has different electrical resistance characteristics when programmed.
摘要翻译：形成集成电路器件的方法包括在衬底上形成至少一个非易失性存储单元。该存储单元包括多个相互电耦合的相变材料区域。该多个可相位改变的材料区域被共同配置为在使用至少四个串行程序电流进行串行编程时支持至少2位的数据。当编程时，多个相变材料区域中的每一个具有不同的电阻特性。

16. 发明申请

US20090016099A1 Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices 有权
标题翻译：具有后编程操作电阻漂移饱和的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法
公开(公告)号：US20090016099A1
公开(公告)日：2009-01-15
申请号：US12079892
申请日：2008-03-28
申请人： Chang-Wook Jeong , Dae-Hwan Kang , Hyeong-Jun Kim , Jae-Min Shin , Seung-Pil Ko
发明人： Chang-Wook Jeong , Dae-Hwan Kang , Hyeong-Jun Kim , Jae-Min Shin , Seung-Pil Ko
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5678 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/0078
摘要： In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.
摘要翻译：在存储器件和其编程方法中，存储器件包括：多个存储器单元，每个存储器单元包括电阻可变材料，该电阻可变材料具有响应于在一个应用编程电流中确定的初始电阻编程操作; 以及修改电路，其在存储单元的编程操作之后修改存储单元的电阻，以通过在饱和运算中施加饱和电流来将存储单元的电阻从初始电阻改变为第二电阻。每个存储单元连接到存储器件的导线，该导线用于施加编程电流以对编程操作中对应的存储单元的电阻进行编程，用于将饱和电流施加到相应的存储单元中饱和操作，并且用于在随后的读取操作中应用读取电流来读取相应存储器单元的电阻。

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