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11. 发明授权

US07721090B1 Event-driven simulation of IP using third party event-driven simulators 有权
标题翻译：使用第三方事件驱动模拟器进行事件驱动的IP仿真
公开(公告)号：US07721090B1
公开(公告)日：2010-05-18
申请号：US11370116
申请日：2006-03-07
申请人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
发明人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
IPC分类号： H04L29/06 , G06F21/00 , G06F12/14 , G06F17/50
CPC分类号： G06F21/12 , G06F17/5022 , G06F21/10 , G06F21/76 , G06F2217/66
摘要： A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.
摘要翻译：创建用于与基于软件的模拟器一起使用的电路设计的安全知识产权（IP）表示的方法可以包括将电路设计的硬件描述语言表示转换为加密的中间形式并编译电路设计的中间形式以产生加密的对象代码。该方法还可以包括将加密的对象代码与仿真内核库链接，从而创建电路设计的安全IP表示。安全IP可以包括电路设计的加密仿真模型和被配置为执行加密仿真模型的仿真内核。

12. 发明授权

US07310594B1 Method and system for designing a multiprocessor 有权
标题翻译：用于设计多处理器的方法和系统
公开(公告)号：US07310594B1
公开(公告)日：2007-12-18
申请号：US10295687
申请日：2002-11-15
申请人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
发明人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/86
摘要： A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.
摘要翻译：多处理器系统（10）包括多个处理引擎（14,16,18,20,22,32,33和35），其包括软件处理引擎和在由单个编程定义的单个硅器件上实现的硬件处理引擎语言和使用至少一个宏标记的单一编程语言。多处理器系统还包括由单个编程语言定义的多个处理引擎与由至少一个宏标记的单个编程语言之间的连接（37和40）。

13. 发明授权

US06630841B2 Configurable logic element with expander structures 有权
公开(公告)号：US06630841B2
公开(公告)日：2003-10-07
申请号：US10097522
申请日：2002-03-12
申请人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
发明人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
IPC分类号： H01L2500
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

14. 发明授权

US06603332B2 Configurable logic block for PLD with logic gate for combining output with another configurable logic block 有权
公开(公告)号：US06603332B2
公开(公告)日：2003-08-05
申请号：US10008556
申请日：2001-11-09
申请人： Alireza S. Kaviani , Sundararajarao Mohan , Ralph D. Wittig , Steven P. Young , Bernard J. New
发明人： Alireza S. Kaviani , Sundararajarao Mohan , Ralph D. Wittig , Steven P. Young , Bernard J. New
IPC分类号： H03K19177
CPC分类号： H03K19/17728
摘要： An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

15. 发明授权

US06400180B2 Configurable lookup table for programmable logic devices 有权
标题翻译：可编程逻辑器件的可配置查找表
公开(公告)号：US06400180B2
公开(公告)日：2002-06-04
申请号：US09861261
申请日：2001-05-18
申请人： Ralph D. Wittig , Sundararajarao Mohan , Bernard J. New
发明人： Ralph D. Wittig , Sundararajarao Mohan , Bernard J. New
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
摘要翻译：用于现场可编程门阵列（FPGA）的可配置逻辑元件（CLE）包括“扩展器”，即允许逻辑块之间的快速信号通信的连接器。扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL，查找表，多路复用器，三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。一个实施例包括可配置逻辑块。在第一模式中，逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。然后使用扩展器组合输出以产生（N + 1） - 输入功能。在第二模式中，逻辑块提供具有M个非共享输入的两个N输入LUT。可选的第三模式基于N个输入信号的值提供多个产品项输出信号。

16. 发明授权

US06388466B1 FPGA logic element with variable-length shift register capability 有权
标题翻译：具有可变长度移位寄存器能力的FPGA逻辑元件
公开(公告)号：US06388466B1
公开(公告)日：2002-05-14
申请号：US09844042
申请日：2001-04-27
申请人： Ralph D. Wittig , Sundararajarao Mohan , Bernard J. New
发明人： Ralph D. Wittig , Sundararajarao Mohan , Bernard J. New
IPC分类号： H03K19177
CPC分类号： H03K19/17728 , H03K19/1736 , H03K19/1737
摘要： A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.
摘要翻译：可编程逻辑器件（PLD）的逻辑元件可以被配置为可变长度的移位寄存器。逻辑元件中的一组存储单元被分成两部分或更多部分。每个部分的存储单元将值提供给相应的输出多路复用电路，从而使逻辑元件能够通过组合多路复用电路的输出作为查找表。然而，每个部分也可配置为移位寄存器。这些部分可以用作单独的移位寄存器，或者可以连接起来作为单个移位寄存器。在一些实施例中，这些部分也可以与其它逻辑元件中的移位寄存器连接。由于两个或多个输出多路复用电路可用，所以提供两个或更多个抽头，一个来自存储器阵列的每个部分。

17. 发明授权

US06292925B1 Context-sensitive self implementing modules 失效
标题翻译：上下文敏感的自我实施模块
公开(公告)号：US06292925B1
公开(公告)日：2001-09-18
申请号：US09049891
申请日：1998-03-27
申请人： Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
发明人： Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. SIMs are called “self implementing” because they encapsulate much of their own implementation information, including mapping, placement, and (optionally) routing information. Therefore, implementing a SIM-based design is significantly faster than with traditional modules, since much of the implementation is already complete and incorporated in the SIM.
摘要翻译：本发明提供了用于可编程逻辑器件（如FPGA）中的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。 SIM在设计时进行自己的设计，根据可能包括所需时序，数据宽度，FIR滤波器的抽头数等的指定参数来针对指定的FPGA。 SIM被称为“自我实施”，因为它们封装了大量自己的实现信息，包括映射，放置和（可选）路由信息。因此，实施基于SIM卡的设计比传统模块要快得多，因为大部分实现已经完成并被并入SIM卡中。

18. 发明授权

US08479042B1 Transaction-level lockstep 有权
标题翻译：事务级锁定步骤
公开(公告)号：US08479042B1
公开(公告)日：2013-07-02
申请号：US12916904
申请日：2010-11-01
申请人： Philip B. James-Roxby , Ralph D. Wittig
发明人： Philip B. James-Roxby , Ralph D. Wittig
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： An embodiment of a method for a high-assurance operation is disclosed. For this embodiment of the method, a first processor and a second processor are clocked for lockstep operation. A first physical address and a first transaction request are provided to a shared bus from the first processor. A second physical address and a second transaction request are provided to the shared bus from the second processor. The first physical address, the first transaction request, the second physical address, and the second transaction request are passed to a proxy device coupled to the shared bus. The first processor and the second processor are proxy served by the proxy device including generation of a third transaction request and a third physical address by the proxy device.
摘要翻译：公开了一种用于高保证操作的方法的实施例。对于该方法的该实施例，第一处理器和第二处理器被计时以进行锁步操作。从第一处理器向共享总线提供第一物理地址和第一事务请求。从第二处理器向共享总线提供第二物理地址和第二事务请求。第一物理地址，第一事务请求，第二物理地址和第二事务请求被传递到耦合到共享总线的代理设备。第一处理器和第二处理器是代理服务的代理服务器，包括由代理设备产生第三事务请求和第三物理地址。

19. 发明授权

US07111273B1 Softpal implementation and mapping technology for FPGAs with dedicated resources 有权
标题翻译：具有专用资源的FPGA的Softpal实现和映射技术
公开(公告)号：US07111273B1
公开(公告)日：2006-09-19
申请号：US10613904
申请日：2003-07-03
申请人： Satish R. Ganesan , Sundararajarao Mohan , Ralph D. Wittig
发明人： Satish R. Ganesan , Sundararajarao Mohan , Ralph D. Wittig
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.
摘要翻译：描述了一个softPAL实现和映射方法。该实现利用LUT和特定于架构的逻辑电路来实现softPAL功能，并且从多个实现中进行选择以减少功能实现中的延迟。该方法描述了用于估计2有界子图中的p项的技术，分解方法，LUT和专用逻辑元件的映射策略以及延迟关键路径的优化。

20. 发明授权

US06583645B1 Field programmable optical arrays 有权
标题翻译：现场可编程光学阵列
公开(公告)号：US06583645B1
公开(公告)日：2003-06-24
申请号：US09940992
申请日：2001-08-27
申请人： David W. Bennett , Sundararajarao Mohan , Ralph D. Wittig
发明人： David W. Bennett , Sundararajarao Mohan , Ralph D. Wittig
IPC分类号： H03K19177
CPC分类号： G02B6/3508 , G02B6/3536 , G02B6/3556
摘要： An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the optical signals. Lookup tables convert optical input signals to electrical signals for selecting values in the lookup table.
摘要翻译：使用光波导描述FPGA，用于通过FPGA路由信号。路由是电气控制的。耦合波导或谐振盘可以用于路由光信号。查找表将光输入信号转换为电信号，用于在查找表中选择值。

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