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11. 发明授权

US5429980A Method of forming a stacked capacitor using sidewall spacers and local oxidation 失效
标题翻译：使用侧壁间隔物和局部氧化形成堆叠电容器的方法
公开(公告)号：US5429980A
公开(公告)日：1995-07-04
申请号：US318423
申请日：1994-10-05
申请人： Ming-Tzong Yang , Anchor Chen , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Anchor Chen , Chen-Chiu Hsue
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L21/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , Y10S438/947
摘要： A method for fabricating a capacitors on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a field effect transistor (FET), having one capacitor aligned over and contacting the source/drain of the FET in the device region. The capacitor is increased in capacitance by forming a double recess in the bottom electrodes of the storage capacitors. The method of forming the double recess utilizes a sidewall spacer and local oxidation technique. After forming the bottom electrode having the double recess an insulating layer having a high dielectric constant is deposited as the inter-electrode insulator and a stop electrode is formed, completing the storage capacitor and the dynamic random access memory (DRAM) storage cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含场效应晶体管（FET），其具有在器件区域中对齐并接触FET的源极/漏极的一个电容器。通过在存储电容器的底部电极中形成双重凹槽，电容器增加电容。形成双凹槽的方法利用侧壁间隔件和局部氧化技术。在形成具有双凹槽的底部电极之后，沉积具有高介电常数的绝缘层作为电极间绝缘体并形成停止电极，从而完成存储电容器和动态随机存取存储器（DRAM）存储单元。

12. 发明授权

US5380676A Method of manufacturing a high density ROM 失效
标题翻译：制造高密度ROM的方法
公开(公告)号：US5380676A
公开(公告)日：1995-01-10
申请号：US247680
申请日：1994-05-23
申请人： Chen-Chiu Hsue , Ming-Tzong Yang , Te-Sun Wu
发明人： Chen-Chiu Hsue , Ming-Tzong Yang , Te-Sun Wu
IPC分类号： H01L21/8246 , H01L21/70
CPC分类号： H01L27/112
摘要： A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.
摘要翻译：通过在衬底上沉积由选自多晶硅和多晶硅化物的材料构成的第一层来形成ROM，通过掩模和蚀刻对第一层进行图案化，在第一层上沉积介电层，并将介电层和第一层图案化成形成第一导体线的图案，通过介电层形成接触窗口，直到衬底，在器件上沉积由选自多晶硅和多晶硅化物的材料组成的第二层，并形成与由第一导线形成的第一导体线正交的第二导体线第一层，以及通过第二层离子注入到衬底中，以形成电连接到第二层的第二导体线的接触区域。

13. 发明授权

US5698458A Multiple well device and process of manufacture 失效
标题翻译：多井设备和制造工艺
公开(公告)号：US5698458A
公开(公告)日：1997-12-16
申请号：US680101
申请日：1996-07-15
申请人： Chen-Chiu Hsue , Sun-Chieh Chien , Chung-Yuan Lee , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Sun-Chieh Chien , Chung-Yuan Lee , Ming-Tzong Yang
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823892
摘要： A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.
摘要翻译：一种制造半导体器件的方法包括在所述器件的表面上形成二氧化硅膜，在所述二氧化硅膜的表面上形成氮化硅图案，将离子注入所述衬底中，与所述氮化硅中的至少一些相邻第一极性的阱区的图案，在所述器件上形成掩模，并且将具有相反极性的离子深入离子注入到相反极性的阱区中。

14. 发明授权

US5572056A High density ROM 失效
标题翻译：高密度ROM
公开(公告)号：US5572056A
公开(公告)日：1996-11-05
申请号：US368146
申请日：1994-12-29
申请人： Chen-Chiu Hsue , Ming-Tzong Yang , Te-Sun Wu
发明人： Chen-Chiu Hsue , Ming-Tzong Yang , Te-Sun Wu
IPC分类号： H01L21/8246 , H01L29/76
CPC分类号： H01L27/112
摘要： A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.
摘要翻译：通过在衬底上沉积由选自多晶硅和多晶硅化物的材料构成的第一层来形成ROM，通过掩模和蚀刻对第一层进行图案化，在第一层上沉积介电层，并将介电层和第一层图案化成形成第一导体线的图案，通过介电层形成接触窗口，直到衬底，在器件上沉积由选自多晶硅和多晶硅化物的材料组成的第二层，并形成与由第一导线形成的第一导体线正交的第二导体线第一层，以及通过第二层离子注入到衬底中，以形成电连接到第二层的第二导体线的接触区域。

15. 发明授权

US5318921A Method for making a high density ROM or EPROM integrated circuit 失效
标题翻译：制造高密度ROM或EPROM集成电路的方法
公开(公告)号：US5318921A
公开(公告)日：1994-06-07
申请号：US55867
申请日：1993-05-03
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L21/8246 , H01L21/70 , H01L27/00
CPC分类号： H01L27/1122 , H01L21/768
摘要： An insulating layer structure is formed over semiconductor device structures in and on a semiconductor substrate. A conductive polysilicon layer covers the insulating layer which is covered by a silicon oxide layer. The oxide layer is now patterned by lithography and etching. This patterning leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form closely spaced polysilicon conductor lines. The silicon oxide layers over the polysilicon conductor lines are removed as by etching. N+ ions are implanted into the silicon substrate under the spacing between the polysilicon conductor lines to form bit lines. An insulating layer structure is formed over the bit lines. Processing continues as before to form a second set of polysilicon lines which form the word lines.
摘要翻译：半导体衬底上半导体器件结构上形成绝缘层结构。导电多晶硅层覆盖被氧化硅层覆盖的绝缘层。氧化层现在通过光刻和蚀刻图案化。该图案在第一指定的多个多晶硅导体线上留下氧化物的第一图案，并且在第二指定的多个多晶硅导体线之间暴露多晶硅层的氧化物加上第一和第二多晶硅导体线之间的预定间隔多晶硅导线。在氧化物层和暴露的多晶硅层上沉积均匀的厚度的氮化硅层，其中厚度是预定间距的宽度。氮化物层被各向异性蚀刻以产生具有预定间隔宽度的侧壁结构。暴露的多晶硅层被氧化。通过蚀刻去除侧壁结构。暴露的多晶硅层被各向异性蚀刻以形成紧密间隔的多晶硅导体线。通过蚀刻去除多晶硅导体线上的氧化硅层。在多晶硅导体线之间的间隔处将N +离子注入到硅衬底中以形成位线。在位线上形成绝缘层结构。处理如前所述继续形成形成字线的第二组多晶硅线。

16. 发明授权

US5712500A Multiple cell with common bit line contact and method of manufacture thereof 失效
标题翻译：具有通用位线接触的多单元及其制造方法
公开(公告)号：US5712500A
公开(公告)日：1998-01-27
申请号：US556326
申请日：1996-02-26
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L23/528 , H01L29/788
CPC分类号： H01L23/5283 , H01L21/768 , H01L2924/0002
摘要： In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterned mask with a second set of openings therein and etching portions of the second word line layer therethrough, h) forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor substrate of the device, the dopant being of sufficient concentration to form a doped region therein.
摘要翻译：根据本发明，半导体存储器件的制造方法包括以下步骤：在半导体衬底上形成场氧化物结构，在衬底的暴露表面上形成栅氧化层，在器件上形成第一字线层通过在其中形成具有第一组开口的第一图案化掩模掩模来形成第一字线层，并通过第一掩模中的开口蚀刻第一字线层以形成导体线，在第一掩模掩模的表面上形成第一介电层在所述器件上的第一字线层，在所述第一电介质层上形成第二字线层，通过在其中形成具有第二组开口的第二组开口形成第二图案化掩模来构图所述第二字线层，并且通过其蚀刻所述第二字线层的部分， h）在所述器件上的所述第二字线层的表面上形成第二电介质层，以及将掺杂剂的离子注入预定位置i n到器件的半导体衬底，掺杂剂具有足够的浓度以在其中形成掺杂区域。

17. 发明授权

US5516713A Method of making high coupling ratio NAND type flash memory 失效
标题翻译：制造高耦合率NAND型闪存的方法
公开(公告)号：US5516713A
公开(公告)日：1996-05-14
申请号：US301533
申请日：1994-09-06
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A new method of fabricating a high coupling ratio Flash EEPROM memory cell is described. A layer of silicon dioxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. The silicon dioxide layer not covered by the patterned silicon nitride layer and the silicon nitride spacers is removed thereby exposing portions of the semiconductor substrate as tunneling windows. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer which is patterned to form a control gate. Passivation and metallization complete the fabrication of the NAND type memory cell with improved coupling ratio.
摘要翻译：描述了制造高耦合比闪存EEPROM存储单元的新方法。在半导体衬底的表面上生长一层二氧化硅。一层氮化硅沉积在二氧化硅层上并构图。在图案化氮化硅层的侧壁上形成氮化硅间隔物。未图案化的氮化硅层和氮化硅间隔层被覆盖的二氧化硅层被去除，从而将半导体衬底的部分暴露为隧道窗。在半导体衬底的暴露部分上生长隧道氧化物层。去除氮化硅层和间隔物。第一多晶硅层沉积在二氧化硅和隧道氧化物层的表面上并被图案化以形成浮栅。在图案化的第一多晶硅层上沉积多层介电层，随后是第二多晶硅层，其被图案化以形成控制栅极。钝化和金属化完成了具有改进的耦合比的NAND型存储单元的制造。

18. 发明授权

US5461251A Symmetric SRAM cell with buried N+ local interconnection line 失效
标题翻译：具有埋地N +局部互连线的对称SRAM单元
公开(公告)号：US5461251A
公开(公告)日：1995-10-24
申请号：US294850
申请日：1994-08-29
申请人： Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L23/535 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1108 , H01L23/535 , H01L27/11 , H01L27/1112 , H01L2924/0002 , Y10S257/903
摘要： A symmetrical, SRAM silicon device comprises a substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no 45.degree. layout, and the metal rule is loose. Pass transistor source and drain regions are formed in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate above the gate oxide juxtaposed with the source region and drain region.
摘要翻译：一种对称的SRAM硅器件包括一个衬底，该衬底包括半导体材料，该硅衬底具有一组掩埋的局部互连线。字线位于设备表面的中央。下拉晶体管对称地位于字线的任一侧。互连在与BN +扩散相同的层中形成。只有一条由多晶硅组成的字线。下拉晶体管位于字线的相对侧。电池尺寸很小没有45°布局，金属规则松散。在与掩埋的局部互连线并置的衬底中形成通过晶体管源极和漏极区。在源极区和漏极区上方有一层栅极氧化物，并且栅极氧化物上方的栅极与源极区和漏极区并置。

19. 发明授权

US5438009A Method of fabrication of MOSFET device with buried bit line 失效
标题翻译：具有掩埋位线的MOSFET器件的制造方法
公开(公告)号：US5438009A
公开(公告)日：1995-08-01
申请号：US100307
申请日：1993-04-02
申请人： Ming-Tzong Yang , Gary Hong
发明人： Ming-Tzong Yang , Gary Hong
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10808
摘要： A doped FET DRAM includes a silicon substrate, with a buried bit line in the silicon substrate. A plug extends down through the substrate to the bit line. A source region and a drain region are positioned above the plug in the substrate with one thereof connected to the plug with a layer of gate oxide above the source region and drain region. A gate above the gate oxide is juxtaposed with the source region and drain region. The source is connected to a capacitor formed of two layers of polysilicon separated by a dielectric of an ONO oxide layer.
摘要翻译：掺杂FET DRAM包括在硅衬底中具有掩埋位线的硅衬底。插头通过衬底向下延伸到位线。源极区域和漏极区域位于衬底上的插塞上方，其中一个源极与源极区域和漏极区域上方连接有栅极氧化物层。栅极氧化物上方的栅极与源区和漏区并列。源极连接到由由ONO氧化物层的电介质隔开的两层多晶硅形成的电容器。

20. 发明授权

US5449644A Process for contact hole formation using a sacrificial SOG layer 失效
标题翻译：使用牺牲SOG层的接触孔形成方法
公开(公告)号：US5449644A
公开(公告)日：1995-09-12
申请号：US181298
申请日：1994-01-13
申请人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
发明人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , Y10S148/133
摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.
摘要翻译：描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

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