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11. 发明授权

US08420466B2 Method of forming TFT floating gate memory cell structures 有权
标题翻译：形成TFT浮栅存储单元结构的方法
公开(公告)号：US08420466B2
公开(公告)日：2013-04-16
申请号：US12259165
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/44 , H01L29/76 , H01L29/788
CPC分类号： H01L29/788 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供一种具有薄膜晶体管（TFT）浮动栅极存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。所述一个或多个源区或漏区中的每一个包括在第一导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层和P-多晶硅层上的浮置栅极。浮栅是由底部氧化物隧道层和上部氧化物阻挡层夹在中间的低压CVD沉积硅层。此外，该器件包括至少一个由覆盖在上氧化物块层上的P +多晶硅层制成的控制栅极。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

12. 发明申请

US20120168860A1 TRANSISTOR AND METHOD FOR FORMING THE SAME 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US20120168860A1
公开(公告)日：2012-07-05
申请号：US13196671
申请日：2011-08-02
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L29/1054 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.
摘要翻译：本发明提供了一种形成晶体管的方法，其包括：提供衬底，在衬底上形成半导体层; 在半导体层上形成虚拟栅极结构; 在衬底和半导体层以及虚拟栅极结构的相对侧形成源区和漏区; 在所述半导体层上形成层间绝缘层; 去除用于在层间电介质层中形成开口的伪栅极结构; 在形成沟道层的开口中暴露的半导体层不结晶; 使沟道层退火，使得沟道层和衬底具有相同的晶体取向; 以及在所述开口中形成金属栅极结构，所述金属栅极形成在所述沟道层上。提高晶体管的饱和电流，提高半导体器件的性能。

13. 发明授权

US08158512B2 Atomic layer deposition method and semiconductor device formed by the same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US08158512B2
公开(公告)日：2012-04-17
申请号：US12141040
申请日：2008-06-17
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Sean Fuxiong Zhang
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Sean Fuxiong Zhang
IPC分类号： H01L21/203
CPC分类号： C23C16/45529 , H01L21/28282 , H01L29/1608 , H01L29/42348 , H01L29/792
摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：在ALD室内使第一前体气体流到半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 形成第一电介质层以覆盖离散化合物单层; 在第一介电层上形成第二第三单层; 并形成第二离散化合物单层; 以及形成第二电介质层以覆盖所述第一电介质层上方的所述第二离散化合物单层。还提供了通过ALD方法形成的半导体器件。

14. 发明授权

US07670900B2 Method and structure for fabricating capacitor devices for integrated circuits 有权
标题翻译：集成电路制造电容器件的方法和结构
公开(公告)号：US07670900B2
公开(公告)日：2010-03-02
申请号：US11549118
申请日：2006-10-13
申请人： Roger Lee , Guoqing Chen , Fumitake Mieno
发明人： Roger Lee , Guoqing Chen , Fumitake Mieno
IPC分类号： H01L21/8242
CPC分类号： H01L28/84 , H01L27/10852
摘要： A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface. The device also has a doped polysilicon layer overlying the inner region of the trench structure. The device has a first hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and a second hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure. In a preferred embodiment, the first grain dimension has an average size of no greater than about ½ of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.
摘要翻译：包括电容器结构的动态随机存取存储器件，例如沟槽，堆叠。该器件包括具有表面区域的衬底（例如，硅，绝缘体上的硅，外延硅）。该器件包括覆盖表面区域的层间电介质区域。在优选实施例中，层间电介质区域具有上表面和下表面。该器件在层间电介质区域的一部分内具有容器结构。容器结构从上表面延伸到下表面。容器结构在上表面具有第一宽度，在下表面具有第二宽度。容器结构具有从上表面延伸到下表面的内部区域。在具体实施方案中，容器结构在下表面附近的内部区域的一部分内部和靠近下表面的内部区域的一部分上具有较高的掺杂剂浓度。器件还具有覆盖在沟槽结构的内部区域上的掺杂多晶硅层。该器件具有第一半球形晶体硅材料，其具有靠近下表面附近的第一晶粒尺寸和在容器结构的上表面附近具有第二晶粒尺寸的第二半球形晶粒硅材料。在优选实施例中，第一晶粒尺寸具有不大于第二晶粒尺寸平均尺寸的约1/2的平均尺寸，以防止半球形晶粒硅材料的任何部分在下表面附近的任何桥接。

15. 发明申请

US20100001281A1 TFT SAS MEMORY CELL STRUCTURES 有权
标题翻译： TFT SAS存储器单元结构
公开(公告)号：US20100001281A1
公开(公告)日：2010-01-07
申请号：US12259144
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/517 , H01L29/66757 , H01L29/66833 , H01L29/792
摘要： A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N− polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P− polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供一种具有薄膜晶体管（TFT）硅 - 氧化铝 - 硅（SAS）存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。一个或多个源极或漏极区域中的每一个在扩散阻挡层上包括位于导电层上的N多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P-多晶硅层上的氧化铝层; 以及覆盖氧化铝层的至少一个控制栅极。在具体实施例中，控制栅由高掺杂P +多晶硅制成。提供了用于制造TFT SAS存储单元结构的方法，并且可以重复三维地集成结构。

16. 发明授权

US07615475B2 Method for fabricating landing polysilicon contact structures for semiconductor devices 有权
标题翻译：制造半导体器件着陆多晶硅接触结构的方法
公开(公告)号：US07615475B2
公开(公告)日：2009-11-10
申请号：US11609758
申请日：2006-12-12
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/3205
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/3162 , H01L21/7684 , H01L21/76895 , H01L21/76897 , H01L27/105 , H01L27/1052
摘要： A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms a cap layer (e.g., silicon nitride, silicon oxynitride) overlying the polysilicon layer. The method forms an Al2O3 layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al2O3 layer. The method includes patterning the sandwich layer to form a plurality of gate structures. Each of the gate structures includes a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al2O3 layer. The method forms an interlayer dielectric material (e.g., BPSG, FSG) having an upper surface overlying the plurality of gate structures. The method also includes patterning the interlayer dielectric material to form an opening in a portion of the interlayer dielectric material to expose each of the gate structures and filling the opening with a polysilicon fill material to a vicinity of the upper surface of the interlayer dielectric material. Preferably, the fill material is doped using an impurity. The method also performs a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer concurrently with a portion of the polysilicon fill material and maintains the chemical mechanical polishing process until a portion of the Al2O3 layer overlying one of the gate structures has been exposed. The method uses portions of the Al2O3 layer as a polish stop while preventing any exposure of any portion of the polysilicon layer.
摘要翻译：一种用于形成集成电路装置的方法，例如存储器，逻辑。该方法包括提供包括表面区域并形成覆盖在表面区域上的多晶硅层的半导体衬底（例如，硅晶片）。优选地，多晶硅层掺杂有杂质以提供导电特性。该方法形成覆盖多晶硅层的覆盖层（例如氮化硅，氮氧化硅）。该方法使用覆盖多晶硅层的原子层沉积形成Al 2 O 3层，以形成包括多晶硅层，盖层和Al 2 O 3层的夹层结构。该方法包括图案化夹层以形成多个栅极结构。每个栅极结构包括多晶硅层的一部分，盖层的一部分和Al 2 O 3层的一部分。该方法形成具有覆盖多个栅极结构的上表面的层间绝缘材料（例如，BPSG，FSG）。该方法还包括图案化层间电介质材料以在层间电介质材料的一部分中形成开口，以露出每个栅极结构，并用多晶硅填充材料填充开口到层间电介质材料的上表面附近。优选地，使用杂质掺杂填充材料。该方法还执行化学机械抛光工艺以与多晶硅填充材料的一部分同时去除一部分层间电介质层，并保持化学机械抛光工艺，直到覆盖其中一个栅极结构的部分Al 2 O 3层已暴露。该方法使用Al 2 O 3层的部分作为抛光停止，同时防止多晶硅层的任何部分的任何暴露。

17. 发明申请

US20080315293A1 Atomic Layer Deposition Method and Semiconductor Device Formed by the Same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US20080315293A1
公开(公告)日：2008-12-25
申请号：US12141045
申请日：2008-06-17
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
IPC分类号： H01L21/28 , H01L29/792
CPC分类号： H01L21/0228 , C23C16/45529 , H01L21/0214 , H01L21/0217 , H01L21/02211 , H01L21/28282 , H01L21/3141 , H01L21/31645 , H01L21/318 , H01L21/3185 , H01L27/11563
摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的电介质层。

18. 发明申请

US20070077356A1 Method for atomic layer deposition of materials using an atmospheric pressure for semiconductor devices 有权
标题翻译：用于半导体器件的大气压原子层沉积材料的方法
公开(公告)号：US20070077356A1
公开(公告)日：2007-04-05
申请号：US11243735
申请日：2005-10-04
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： C23C16/00
CPC分类号： C23C16/403 , C23C16/45525 , C23C16/45551
摘要： A method for atomic layer deposition. The method includes providing a substrate having a surface region and exposing the surface region of the substrate to an atmospheric pressure. The method also maintains at least the substrate at about the atmospheric pressure and forms a film overlying the surface region using atomic layer deposition, while the substrate is maintained at about atmospheric pressure. Preferably, the film is grown at a rate of greater than about 1 nanometer per minute.
摘要翻译：一种原子层沉积的方法。该方法包括提供具有表面区域并将衬底的表面区域暴露于大气压的衬底。该方法还在大气压附近至少保持基板，并且使用原子层沉积形成覆盖表面区域的膜，同时将基板保持在大气压附近。优选地，膜以大于约1纳米每分钟的速率生长。

19. 发明申请

US20070071894A1 METHOD FOR ATOMIC LAYER DEPOSITION OF MATERIALS USING A PRE-TREATMENT FOR SEMICONDUCTOR DEVICES 有权
标题翻译：使用半导体器件预处理的材料的原子层沉积方法
公开(公告)号：US20070071894A1
公开(公告)日：2007-03-29
申请号：US11536472
申请日：2006-09-28
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： C23C16/00
CPC分类号： C23C16/0227
摘要： A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing an oxidizing species into the chamber. The method includes treating the upper surface of the semiconductor substrate to remove the one or more carbon bearing species and form a particle film of silicon dioxide overlying the upper surface. The method includes introducing an inert gas into the chamber to purge the chamber of the oxidizing species and other species associated with the one or more carbon bearing species. A reducing species is introduced into the chamber to strip the particle film of silicon dioxide to create a substantially clean surface treated with hydrogen bearing species. The method includes performing another process (e.g., atomic layer deposition) on the substantially clean surface while the substrate is maintained in a vacuum environment. The substantially clean surface is substantially free from native oxide and carbon bearing particles.
摘要翻译：一种形成原子层沉积的方法。该方法包括将包括上表面的半导体衬底（例如，晶片，LCD面板）放置在腔室中。上表面包括一个或多个碳承载物质和天然氧化物层。该方法包括将氧化物质引入室中。该方法包括处理半导体衬底的上表面以除去一种或多种含碳物质并形成覆盖在上表面上的二氧化硅的颗粒膜。该方法包括将惰性气体引入室中以净化氧化物质的室和与一种或多种含碳物质相关联的其它物质。将还原物质引入室中以剥离二氧化硅的颗粒膜以产生用含氢物质处理的基本上清洁的表面。该方法包括在基板保持在真空环境中时在基本上清洁的表面上执行另一工艺（例如，原子层沉积）。基本上干净的表面基本上不含有自然氧化物和碳的颗粒。

20. 发明授权

US5843829A Method for fabricating a semiconductor device including a step for forming an amorphous silicon layer followed by a crystallization thereof 失效
标题翻译：一种制造半导体器件的方法，包括用于形成非晶硅层的步骤，接着进行结晶
公开(公告)号：US5843829A
公开(公告)日：1998-12-01
申请号：US559813
申请日：1995-11-17
申请人： Masaki Kuramae , Fumitake Mieno
发明人： Masaki Kuramae , Fumitake Mieno
IPC分类号： C23C16/52 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L21/2022 , H01L28/84 , H01L28/87 , Y10S438/901
摘要： A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在衬底上沉积非晶硅层，并通过用氧化气体处理非晶硅层的表面，在非晶硅层的表面上形成氧化膜。形成步骤在非晶硅层结晶之前发生。

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