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11. 发明授权

US06414883B2 Semiconductor memory device 失效
公开(公告)号：US06414883B2
公开(公告)日：2002-07-02
申请号：US09860795
申请日：2001-05-21
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

12. 发明授权

US6075732A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US6075732A
公开(公告)日：2000-06-13
申请号：US334917
申请日：1999-06-17
申请人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
CPC分类号： G11C29/806 , G11C29/781 , G11C8/10
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译：半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE）），并且由行解码器组（4a，4b）选择有缺陷的行。每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。

13. 再颁专利

USRE36089E Column selecting circuit in semiconductor memory device 失效
标题翻译：半导体存储器件中的列选择电路
公开(公告)号：USRE36089E
公开(公告)日：1999-02-09
申请号：US652008
申请日：1996-05-23
申请人： Tsukasa Ooishi , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi , Shinji Kawai , Mikio Asakura , Masaki Tsukude , Katsuhiro Suma , Shigeki Tomishima , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi , Shinji Kawai , Mikio Asakura , Masaki Tsukude , Katsuhiro Suma , Shigeki Tomishima , Kazuyasu Fujishima
IPC分类号： G11C11/407 , G11C7/10 , G11C8/12 , G11C11/401 , G11C11/41 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C8/12 , G11C7/10
摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.
摘要翻译：列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。这导致每个预解码信号线的布线长度被缩短。

14. 发明授权

US5504713A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US5504713A
公开(公告)日：1996-04-02
申请号：US180166
申请日：1994-01-11
申请人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译：半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S）由行解码器组（4a，4b）选择。每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。

15. 发明授权

US06859403B2 Semiconductor memory device capable of overcoming refresh disturb 失效
标题翻译：能够克服刷新干扰的半导体存储器件
公开(公告)号：US06859403B2
公开(公告)日：2005-02-22
申请号：US10815798
申请日：2004-04-02
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.
摘要翻译：第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。第二晶体管在其栅极处接收内部产生的信号，其源极接地。在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

16. 发明授权

US06272055B1 Semiconductor memory device 失效
公开(公告)号：US06272055B1
公开(公告)日：2001-08-07
申请号：US09168962
申请日：1998-10-09
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

17. 发明授权

US5943273A Semiconductor memory device 失效
公开(公告)号：US5943273A
公开(公告)日：1999-08-24
申请号：US899143
申请日：1997-07-23
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4091 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

18. 发明授权

US5687123A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5687123A
公开(公告)日：1997-11-11
申请号：US312968
申请日：1994-09-30
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4091 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.
摘要翻译：第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。第二晶体管在其栅极处接收内部产生的信号，其源极接地。在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

19. 发明授权

US5289417A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US5289417A
公开(公告)日：1994-02-22
申请号：US958466
申请日：1992-10-08
申请人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： G11C29/00
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译：半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在有缺陷行时产生备用行译码器选择信号（S（OVS）），并且有缺陷的行由行解码器组（4a，4b）选择。每个备用行解码器（5a，5b）响应于备用行解码器选择信号（S（OVS））和块控制信号被激活。

20. 发明授权

US5249155A Semiconductor device incorporating internal voltage down converting circuit 失效
标题翻译：包含内部电压降低转换电路的半导体器件
公开(公告)号：US5249155A
公开(公告)日：1993-09-28
申请号：US819208
申请日：1992-01-10
申请人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
发明人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
IPC分类号： H01L21/8234 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/11 , H03K17/30
CPC分类号： H03K17/302 , G05F1/465 , G11C5/147 , H01L2924/0002
摘要： An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.
摘要翻译：由N沟道MOS晶体管构成的n沟道驱动电路与由P沟道MOS晶体管构成的驱动电路并联设置。通常，n通道驱动电路提供内部电源电压，仅在当前峰值时激活驱动电路。因此，补充了n沟道驱动电路不足以提供电流的能力。

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