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11. 发明授权

US6165835A Method for producing a silicon capacitor 失效
标题翻译：硅电容器的制造方法
公开(公告)号：US6165835A
公开(公告)日：2000-12-26
申请号：US341937
申请日：1999-07-20
申请人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
发明人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10861 , H01L29/66181 , Y10S438/96
摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.
摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质层（4）和导电层（5），而不填充孔结构（2）。为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面压缩机械应力。

12. 发明授权

US5347696A Method for manufacturing a multi-layer capacitor 失效
标题翻译：多层电容器的制造方法
公开(公告)号：US5347696A
公开(公告)日：1994-09-20
申请号：US164719
申请日：1993-12-10
申请人： Josef Willer , Hermann Wendt , Hans Reisinger
发明人： Josef Willer , Hermann Wendt , Hans Reisinger
IPC分类号： C23F4/00 , H01G4/30 , H01L21/822 , H01L27/04 , H01G4/10
CPC分类号： H01G4/306 , Y10T29/435
摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).
摘要翻译：为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层（2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

13. 发明授权

US07049651B2 Charge-trapping memory device including high permittivity strips 有权
标题翻译：电荷捕获存储器件包括高电容率带
公开(公告)号：US07049651B2
公开(公告)日：2006-05-23
申请号：US10715142
申请日：2003-11-17
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

14. 发明授权

US06627940B1 Memory cell arrangement 失效
标题翻译：存储单元布置
公开(公告)号：US06627940B1
公开(公告)日：2003-09-30
申请号：US09937838
申请日：2002-02-05
申请人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
发明人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.
摘要翻译：存储单元阵列包括形成平行的第一和第二沟槽的衬底。晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。绝缘空间横向与字线连接。导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

15. 发明授权

US07402490B2 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US07402490B2
公开(公告)日：2008-07-22
申请号：US11253939
申请日：2005-10-19
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
摘要翻译：为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。栅电极层被构造成形成具有侧壁的栅电极。执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。然后可以沉积电荷捕获层材料以填充空间。然后在与栅电极相邻的半导体本体中形成源区和漏区。

16. 发明申请

US20060091448A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20060091448A1
公开(公告)日：2006-05-04
申请号：US11253939
申请日：2005-10-19
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
摘要翻译：为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。栅电极层被构造成形成具有侧壁的栅电极。执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。然后可以沉积电荷捕获层材料以填充空间。然后在与栅电极相邻的半导体本体中形成源区和漏区。

17. 发明授权

US06518613B2 Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same 有权
标题翻译：具有在基板相对表面上的电容器的存储单元配置及其制造方法
公开(公告)号：US06518613B2
公开(公告)日：2003-02-11
申请号：US09968304
申请日：2001-10-01
申请人： Josef Willer , Hans Reisinger , Till Schlosser , Reinhard Stengl
发明人： Josef Willer , Hans Reisinger , Till Schlosser , Reinhard Stengl
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/1087
摘要： A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.
摘要翻译：存储单元的MOS晶体管和与其连接的位线设置在基板的第一表面上。存储单元的电容器设置在基板的第二表面上，第二表面与第一表面相对。接触件设置在衬底中并将电容器连接到MOS晶体管。

18. 发明授权

US5500385A Method for manufacturing a silicon capacitor by thinning 失效
标题翻译：通过减薄制造硅电容器的方法
公开(公告)号：US5500385A
公开(公告)日：1996-03-19
申请号：US451534
申请日：1995-05-26
申请人： Hermann Wendt , Josef Willer , Hans Reisinger , Volker Lehmann
发明人： Hermann Wendt , Josef Willer , Hans Reisinger , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/225 , H01L21/334 , H01L21/822 , H01L21/762
CPC分类号： H01L29/66181 , Y10S438/924 , Y10S438/928 , Y10S438/977
摘要： For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an etching proceeding from the back side, this etching attacking silicon selectively to p.sup.+ -doped silicon and therefore stopping when the p.sup.+ -doped region is reached.
摘要翻译：为了制造硅电容器，在n掺杂硅衬底中产生孔开口，在其表面形成p +掺杂区域，并且该表面与导电层一起设置介电层。硅衬底通过从背面进行的蚀刻变薄，该蚀刻选择性地攻击到p +掺杂的硅，因此当达到p +掺杂区域时停止。

19. 发明申请

US20050104117A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20050104117A1
公开(公告)日：2005-05-19
申请号：US10715142
申请日：2003-11-17
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

20. 发明授权

US06995416B2 Memory device for storing electrical charge and method for fabricating the same 失效
标题翻译：用于存储电荷的存储器件及其制造方法
公开(公告)号：US06995416B2
公开(公告)日：2006-02-07
申请号：US10853734
申请日：2004-05-26
申请人： Hans Reisinger , Reinhard Stengl , Herbert Schäfer
发明人： Hans Reisinger , Reinhard Stengl , Herbert Schäfer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , H01L27/10814 , H01L27/10852 , H01L28/91 , H01L51/0048 , H01L51/0052 , Y10S977/842 , Y10S977/943
摘要： The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.
摘要翻译：本发明提供一种用于存储电荷的存储装置，其具有作为存储元件的施加在电极层上并连接到其上的管元件。管元件设置有电介质涂层，用于填充管元件之间的空间的填充材料。与填充材料连接的对电极形成为在电极层和对电极之间形成用于存储电荷的电容器。管元件有利地包括碳纳米管，结果由于电容器电极表面的面积急剧增加，电容器的电容。

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