专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07761617B2 Multi-threaded DMA 有权
标题翻译：多线程DMA
公开(公告)号：US07761617B2
公开(公告)日：2010-07-20
申请号：US11082564
申请日：2005-03-17
申请人： Franck Seigneret , Sivayya Ayinala , Nabil Khalifa , Praveen Kolli , Prabha Atluri
发明人： Franck Seigneret , Sivayya Ayinala , Nabil Khalifa , Praveen Kolli , Prabha Atluri
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
摘要翻译：直接存储器访问（DMA）电路（200）包括读取端口（202）和写入端口（204）。 DMA电路（200）是具有在读端口（202）上的“m”个线程和写入端口（204）上的“n”个线程的多线程启动器。 DMA电路（200）包括提供更有效的缓冲和流水线化的两个解耦的读和写上下文和调度器（302,304）。调度器（302,304）主要在线程边界处的信道之间进行仲裁。一个线程与一个DMA服务相关联，其中服务可以是单个或突发事务。多线程DMA传输允许并发通道传输。

12. 发明申请

US20090204413A1 METHOD AND SYSTEM FOR ASYMMETRIC INDEPENDENT AUDIO RENDERING 有权
标题翻译：不对称独立音频渲染的方法和系统
公开(公告)号：US20090204413A1
公开(公告)日：2009-08-13
申请号：US12342327
申请日：2008-12-23
申请人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
发明人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
IPC分类号： G10L19/00
CPC分类号： G10L19/16
摘要： Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
摘要翻译：提供了用于片上系统（SOC）中的音频流的非对称独立处理的方法和移动设备。更具体地，针对对SOC执行音频处理的处理器提供独立音频路径，并且通过硬件数字混频器在SOC上数字地执行来自处理器的解码音频样本的混合。

13. 发明授权

US07373437B2 Multi-channel DMA with shared FIFO 有权
标题翻译：具有共享FIFO的多通道DMA
公开(公告)号：US07373437B2
公开(公告)日：2008-05-13
申请号：US11080277
申请日：2005-03-15
申请人： Franck Seigneret , Nabil Khalifa , Sivayya Ayinala , Praveen Kolli
发明人： Franck Seigneret , Nabil Khalifa , Sivayya Ayinala , Praveen Kolli
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
摘要翻译：直接存储器访问（DMA）电路（200）包括读取端口（202）和写入端口（204）。 DMA电路（200）是具有在读端口（202）上的“m”个线程和写入端口（204）上的“n”个线程的多线程启动器。 DMA电路（200）包括由所有逻辑信道共享的数据FIFO（210），并且可以动态地分配FIFO深度，允许调度和同时激活最大数量的信道。如果只有一个逻辑信道有效，则FIFO（210）也可以被分配给单个信道。 FIFO（210）增加DMA的传输性能，预取容量和缓冲，同时最大化流水线。

14. 发明申请

US20070279432A1 Method and Apparatus for Spatial and Temporal Dithering 有权
标题翻译：空间和时间抖动的方法和装置
公开(公告)号：US20070279432A1
公开(公告)日：2007-12-06
申请号：US11611299
申请日：2006-12-15
申请人： Jean Noel , Franck Seigneret
发明人： Jean Noel , Franck Seigneret
IPC分类号： G09G5/02
CPC分类号： G09G5/02 , G09G3/2055
摘要： An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither addend is determined based on the display position of the pixel. The dither addend is added to the color component, and the color component is rounded to a second size. In one embodiment, a first frame may be provided for displaying the first pixel, the dither addend corresponding to the first frame. One or more additional frames for displaying the first pixel are provided, and one or more additional dither addends corresponding to the first pixel in the additional frames may be determined. The dither addend is different from the additional dither addends, and the additional dither addends are different from each other.
摘要翻译：用于空间和时间抖动像素的装置和方法。提供包括至少一个第一尺寸的颜色分量的像素。基于像素的显示位置来确定抖动加数。将抖动加数添加到颜色分量，并将颜色分量四舍五入为第二大小。在一个实施例中，可以提供第一帧以显示第一像素，对应于第一帧的抖动加数。提供用于显示第一像素的一个或多个附加帧，并且可以确定与附加帧中的第一像素对应的一个或多个附加抖动加数。抖动加数与附加抖动加数不同，并且附加抖动加数彼此不同。

15. 发明授权

US06788348B1 Method and system for processing digital images 有权
标题翻译：数字图像处理方法及系统
公开(公告)号：US06788348B1
公开(公告)日：2004-09-07
申请号：US09718076
申请日：2000-11-21
申请人： Emmanuel Chiaruzzi , Franck Seigneret
发明人： Emmanuel Chiaruzzi , Franck Seigneret
IPC分类号： H04N701
CPC分类号： H04N11/20 , H04N9/641
摘要： Transforming digital images including luminance data relating to points with first coordinates and chrominance data relating to points with second coordinates is performed. More particularly, the transforming is performed where one of the luminance data and the chrominance data is more numerous than the other. This is done by processing the least numerous data by filtering to obtain least numerous data relating to points with identical coordinates to those of the most numerous data.
摘要翻译：执行包括与具有第一坐标的点相关的亮度数据和与具有第二坐标的点有关的色度数据的数字图像的变换。更具体地，在亮度数据和色度数据之一比另一个更多的情况下执行变换。这是通过过滤来处理最少的数据来获得与具有相同坐标的点与最多数据数据相关的最少数量数据来完成的。

16. 发明授权

US06744439B1 Reconfigurable color converter 有权
标题翻译：可重构颜色转换器
公开(公告)号：US06744439B1
公开(公告)日：2004-06-01
申请号：US09695753
申请日：2000-10-24
申请人： Marc Laury , Franck Seigneret , Emmanuel Chiaruzzi , Philippe Monnier
发明人： Marc Laury , Franck Seigneret , Emmanuel Chiaruzzi , Philippe Monnier
IPC分类号： G09G537
CPC分类号： G09G5/02 , G09G5/06 , G09G5/393 , G09G2320/0276
摘要： A digital image processing circuit for replacing an input code associated with a pixel of the image with an output code selected in a first memory containing a set of codes, including an input bus for receiving the input code, an output bus for providing the output code, said first memory, means of address calculation of the first memory, means of address selection of the first memory between the input code and an address code generated by the address calculation means, a second memory for containing an address code generated by the address calculation means, and means of selection of the output code between a code read from the first memory and said code contained in the second memory.
摘要翻译：一种数字图像处理电路，用于使用在包含用于接收输入代码的输入总线的第一存储器中选择的输出代码来替换与图像的像素相关联的输入代码，用于提供输出代码的输出总线所述第一存储器，第一存储器的地址计算装置，输入代码和由地址计算装置生成的地址码之间的第一存储器的地址选择装置，用于包含由地址计算产生的地址码的第二存储器以及从第一存储器读取的代码和包含在第二存储器中的所述代码之间的输出代码的选择的装置。

17. 发明授权

US08200479B2 Method and system for asymmetric independent audio rendering 有权
标题翻译：非对称独立音频渲染方法与系统
公开(公告)号：US08200479B2
公开(公告)日：2012-06-12
申请号：US12342327
申请日：2008-12-23
申请人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
发明人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
IPC分类号： G10L19/00 , G10L21/00 , G10L11/00 , G10L19/14
CPC分类号： G10L19/16
摘要： Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
摘要翻译：提供了用于片上系统（SOC）中的音频流的非对称独立处理的方法和移动设备。更具体地，针对对SOC执行音频处理的处理器提供独立音频路径，并且通过硬件数字混频器在SOC上数字地执行来自处理器的解码音频样本的混合。

18. 发明申请

US20110225256A1 Video Synchronization with Distributed Modules 有权
标题翻译：与分布式模块的视频同步
公开(公告)号：US20110225256A1
公开(公告)日：2011-09-15
申请号：US12764448
申请日：2010-04-21
申请人： Franck Seigneret , Claude Marescot , Seyed Karim Djafarian Tehrani , Maija Kuusela , Alain Bruno Chateau
发明人： Franck Seigneret , Claude Marescot , Seyed Karim Djafarian Tehrani , Maija Kuusela , Alain Bruno Chateau
IPC分类号： G06F15/16
CPC分类号： G06F9/4843
摘要： A digital system is provided that includes a number of hardware accelerators. Each hardware accelerator is paired with a synchronization module that is configured to determine when a scheduled task can be started. Each synchronization module includes a network interface configured to send and receive messages to and from other synchronization modules and a configuration interface configured to receive task information from a host processor. Each synchronization module also includes a task scheduler configured to select a task in response to a received message and a task processor interface configured to initiate the selected task on a hardware accelerator coupled to the synchronization module.
摘要翻译：提供了包括多个硬件加速器的数字系统。每个硬件加速器与配置为确定何时可以启动计划任务的同步模块配对。每个同步模块包括被配置为向和从其他同步模块发送消息和从其他同步模块接收消息的网络接口和被配置为从主机处理器接收任务信息的配置接口。每个同步模块还包括被配置为响应于接收到的消息选择任务的任务调度器和配置成在耦合到同步模块的硬件加速器上发起所选任务的任务处理器接口。

19. 发明授权

US07609277B2 Method and apparatus for spatial and temporal dithering 有权
标题翻译：空间和时间抖动的方法和装置
公开(公告)号：US07609277B2
公开(公告)日：2009-10-27
申请号：US11611299
申请日：2006-12-15
申请人： Jean Noel , Franck Seigneret
发明人： Jean Noel , Franck Seigneret
IPC分类号： G09G5/02
CPC分类号： G09G5/02 , G09G3/2055
摘要： An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither addend is determined based on the display position of the pixel. The dither addend is added to the color component, and the color component is rounded to a second size. In one embodiment, a first frame may be provided for displaying the first pixel, the dither addend corresponding to the first frame. One or more additional frames for displaying the first pixel are provided, and one or more additional dither addends corresponding to the first pixel in the additional frames may be determined. The dither addend is different from the additional dither addends, and the additional dither addends are different from each other.
摘要翻译：用于空间和时间抖动像素的装置和方法。提供包括至少一个第一尺寸的颜色分量的像素。基于像素的显示位置来确定抖动加数。将抖动加数添加到颜色分量，并将颜色分量四舍五入为第二大小。在一个实施例中，可以提供第一帧以显示第一像素，对应于第一帧的抖动加数。提供用于显示第一像素的一个或多个附加帧，并且可以确定与附加帧中的第一像素对应的一个或多个附加抖动加数。抖动加数与附加抖动加数不同，并且附加抖动加数彼此不同。

20. 发明授权

US07447349B2 Method and a system for processing digital images 有权
标题翻译：方法和数字图像处理系统
公开(公告)号：US07447349B2
公开(公告)日：2008-11-04
申请号：US10432922
申请日：2001-11-22
申请人： Franck Seigneret
发明人： Franck Seigneret
IPC分类号： G06K9/00
CPC分类号： G06T17/00
摘要： A method for processing digital images includes generating a plurality of images of reduced size from a two-dimensional image, with the reduced sizes being different from each other. The reduced size images are stored in memory. A three-dimensional image is generated in real time from a frame provided with unit surfaces and from pixels chosen from the image and the reduced size images as a function of the orientation of a unit surface to which a pixel is to be assigned.
摘要翻译：一种处理数字图像的方法包括从二维图像生成尺寸减小的多个图像，缩小的尺寸彼此不同。减小尺寸的图像被存储在存储器中。作为与要分配像素的单位表面的取向的函数，从设置有单位表面的帧和从图像和缩小尺寸图像中选择的像素实时地生成三维图像。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式