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    • 18. 发明申请
    • Memory access system and method for optimizing SDRAM bandwidth
    • 用于优化SDRAM带宽的内存访问系统和方法
    • US20120239873A1
    • 2012-09-20
    • US13137643
    • 2011-08-31
    • Ming-Chuan HuangChia-Hao Lee
    • Ming-Chuan HuangChia-Hao Lee
    • G06F12/00
    • G06F13/1626
    • A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.
    • 用于优化SDRAM带宽的存储器访问系统包括存储器命令处理器,以及SDRAM接口和协议控制器。 存储器命令处理器连接到存储器总线仲裁器和数据交换电路,用于接收由存储器总线仲裁器和数据开关电路输出的存储器访问命令,并将存储器访问命令转换为重新排序的SDRAM命令。 SDRAM接口和协议控制器连接到存储器命令处理器,用于基于SDRAM的协议和时序接收和执行重新排序的SDRAM命令。 存储器命令处理器将存储器访问命令解码为通用SDRAM命令或替代的SDRAM命令。 解码为替代SDRAM命令的存储器访问命令由特定总线主机产生。
    • 19. 发明授权
    • Memory test system with advance features for completed memory system
    • 内存测试系统具有完善的内存系统的先进功能
    • US08392768B2
    • 2013-03-05
    • US13064513
    • 2011-03-30
    • Chia-Hao LeeMing-Chuan Huang
    • Chia-Hao LeeMing-Chuan Huang
    • G11C29/00
    • G11C29/56G11C11/401
    • In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.
    • 在具有完成存储器系统的先进特性的存储器测试系统中,硬件组件被独立地配置为产生用于执行可编程加载测试,实际情况测试和写反馈测试的通用测试模式。 写入反馈测试用于独立测试嵌入在集成电路中的存储器控​​制器,而不与外部SDRAM通信。 在集成电路验证阶段,内存测试系统支持分析和区分集成电路内外的问题,并对各个写入和读取命令进行测试。