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11. 发明授权

US6081002A Lateral SCR structure for ESD protection in trench isolated technologies 失效
标题翻译：沟槽隔离技术中ESD保护的横向SCR结构
公开(公告)号：US6081002A
公开(公告)日：2000-06-27
申请号：US85818
申请日：1998-05-27
申请人： E. Ajith Amerasekera , Bernhard H. Andresen , Amitava Chatterjee
发明人： E. Ajith Amerasekera , Bernhard H. Andresen , Amitava Chatterjee
IPC分类号： H01L27/02 , H01L29/74
CPC分类号： H01L27/0259 , H01L27/0266
摘要： A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.
摘要翻译：一种用于沟槽隔离技术的保护装置。保护装置包括横向SCR（100），其包括触发MOS晶体管（120）和与SCR（100）的阴极（112）连接的第一栅电极（116）。横向SCR（100）的阳极（110）通过第二栅电极（132）而不是通过沟槽隔离与触发MOS晶体管（120）的最近的源极/漏极区域（122）分离。通过使用第二栅电极（132）进行隔离而不是沟槽隔离，横向SCR（100）的表面导通不受阻碍。

12. 发明授权

US5930094A Cascoded-MOS ESD protection circuits for mixed voltage chips 有权
标题翻译：用于混合电压芯片的Cascoded-MOS ESD保护电路
公开(公告)号：US5930094A
公开(公告)日：1999-07-27
申请号：US140051
申请日：1998-08-26
申请人： E. Ajith Amerasekera , Raoul B. Salem
发明人： E. Ajith Amerasekera , Raoul B. Salem
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H02H9/04
CPC分类号： H01L27/0251 , H01L27/0266
摘要： Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.
摘要翻译：限定了串联nMOS ESD保护电路中的控制端电压的偏置电路，使得在正常工作期间电路处于高阻态（OFF），并且在ESD事件期间具有低阻抗（ON）。 G1和G2是在焊盘的ESD事件期间定义V3和V4的驱动电路。在正常工作期间，V3和/或V4为高电平，焊盘和VSS之间没有电流流动。在ESD事件期间，V3和V4为高电平，两个器件在外部NPN导通时会导通MOS电流。二极管D1导通电流Cc，芯片电容，提高VDD，使G1和G2导通，并将V3和V4升高到大于nMOS阈值电压的电平。

13. 发明授权

US5804860A Integrated lateral structure for ESD protection in CMOS/BiCMOS technologies 失效
标题翻译： CMOS / BiCMOS技术中ESD保护的集成横向结构
公开(公告)号：US5804860A
公开(公告)日：1998-09-08
申请号：US740596
申请日：1996-10-31
申请人： E. Ajith Amerasekera
发明人： E. Ajith Amerasekera
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L23/62
CPC分类号： H01L27/0248 , H01L27/0259 , H01L27/0266 , Y10S257/93
摘要： One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped region spaced away from the first doped region by the channel region. Preferably, a first bipolar transistor (210) is integrated into the electrostatic discharge device and is formed by the substrate, the lightly-doped region and the second doped region and a second bipolar transistor (212) is integrated into the electrostatic discharge device and is formed by the substrate, the first doped region and the second doped region, the first bipolar transistor becoming conductive at a lower voltage during an ESD event than the second bipolar transistor but the second bipolar transistor able to carry more current during the ESD event.
摘要翻译：本发明的一个实施例是一种静电放电保护装置（10），其包括场效应晶体管，所述场效应晶体管包括：第一导电类型的基板（12），具有表面和背面; 绝缘地设置在所述基板上的栅极结构（18）阻挡区域（30），设置在所述基板上并且邻近所述栅极结构; 第二导电类型的轻掺杂区域（32）与第一导电类型相反并且设置在衬底内并在阻挡区域下方; 沟道区域（14），设置在所述衬底内，栅极结构下方，并且与所述轻掺杂区域相邻; 所述第二导电类型的第一掺杂区域（38）设置在所述衬底内且与所述轻掺杂区域相邻，所述第一掺杂区域通过所述轻掺杂区域与所述沟道区域间隔开; 和第二导电类型的第二掺杂区域（22），并且设置在衬底内，第二掺杂区域通过沟道区域与第一掺杂区域间隔开。优选地，第一双极晶体管（210）被集成到静电放电装置中并且由衬底，轻掺杂区域和第二掺杂区域以及第二双极晶体管（212）形成在静电放电装置中并且是由衬底，第一掺杂区域和第二掺杂区域形成，第一双极晶体管在ESD事件期间以比第二双极晶体管更低的电压导通，但是第二双极晶体管能够在ESD事件期间承载更多的电流。

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