专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08503231B2 Multi-level cell flash memory device and read method 有权
标题翻译：多级单元闪存设备和读取方式
公开(公告)号：US08503231B2
公开(公告)日：2013-08-06
申请号：US12623509
申请日：2009-11-23
申请人： Moo-sung Kim , Pan-suk Kwak
发明人： Moo-sung Kim , Pan-suk Kwak
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading data of a multi-level cell (MLC) flash memory device is disclosed. The method includes reading a least significant bit (LSB) and a most significant bit (MSB) of the data programmed to a plurality of memory cells. Reading each of the LSB and MSB includes; reading a MSB flag indicating whether or not the MSB for memory cells in a page of memory cells has been programmed, performing a first read with respect to a plurality of first bit lines, setting a target voltage in view of the read value of the MSB flag, applying the target voltage to a plurality of second bit lines, and performing a second read with respect to the plurality of second bit lines.
摘要翻译：公开了一种读取多级单元（MLC）闪速存储器件的数据的方法。该方法包括读取编程到多个存储器单元的数据的最低有效位（LSB）和最高有效位（MSB）。读取每个LSB和MSB包括; 读取指示存储器单元页中的存储器单元的MSB是否已被编程的MSB标志，对多个第一位线执行第一次读取，根据MSB的读取值设置目标电压标志，将目标电压施加到多个第二位线，并且对于多个第二位线执行第二读取。

12. 发明授权

US08040726B2 Flash memory device and layout method of the flash memory device 有权
标题翻译：闪存设备的闪存设备和布局方法
公开(公告)号：US08040726B2
公开(公告)日：2011-10-18
申请号：US12506357
申请日：2009-07-21
申请人： Pan-suk Kwak
发明人： Pan-suk Kwak
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/10
摘要： Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.
摘要翻译：提供了一种包括多个页缓冲器高压晶体管的闪存器件。多个高压晶体管与页面缓冲电路可操作地相关联，其中每个高压晶体管包括：将第一图案与第二图案分离的栅极图案。第一和第二图案并行延伸并用作相应的源极/漏极区域，并且第一图案被浮置，并且第二图案在擦除操作期间接收擦除电压。第一组高压晶体管串联连接成柱状布置，使得相邻的高压晶体管列在柱状方向上以交替的源/漏对称布置。

13. 发明申请

US20100128530A1 FLASH MEMORY DEVICE AND LAYOUT METHOD OF THE FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件的闪存存储器和布局方法
公开(公告)号：US20100128530A1
公开(公告)日：2010-05-27
申请号：US12506357
申请日：2009-07-21
申请人： Pan-suk Kwak
发明人： Pan-suk Kwak
IPC分类号： G11C16/04 , G06F17/50
CPC分类号： G11C16/14 , G11C16/10
摘要： Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.
摘要翻译：提供了一种包括多个页缓冲器高压晶体管的闪存器件。多个高压晶体管与页面缓冲电路可操作地相关联，其中每个高压晶体管包括：将第一图案与第二图案分离的栅极图案。第一和第二图案并行延伸并用作相应的源极/漏极区域，并且第一图案被浮置，并且第二图案在擦除操作期间接收擦除电压。第一组高压晶体管串联连接成柱状布置，使得相邻的高压晶体管列在柱状方向上以交替的源/漏对称布置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式