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11. 发明授权

US06448917B1 DAC using current source driving main resistor string 有权
标题翻译： DAC采用电流源驱动主电阻串
公开(公告)号：US06448917B1
公开(公告)日：2002-09-10
申请号：US09668882
申请日：2000-09-25
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M166
CPC分类号： H03M1/0663 , H03M1/682 , H03M1/765
摘要： An digital-to-analog converter having main DAC resistor strings and sub-DAC resistor strings for converting MSB and LSB portions of a digital word into corresponding analog voltages. The main DAC resistor strings are driven by constant current sources to improve the linearity of the conversion process. The constant current sources present a high impedance to the main DAC resistor strings, thereby providing a more linear change in resistance during the conversion process, and reducing second-order harmonic nonlinearity.
摘要翻译：具有主DAC电阻串和子DAC电阻串的数/模转换器，用于将数字字的MSB和LSB部分转换为相应的模拟电压。主DAC电阻串由恒流源驱动，以提高转换过程的线性。恒流源对主DAC电阻串呈现高阻抗，从而在转换过程中提供更线性的电阻变化，并降低二阶谐波非线性。

12. 发明授权

US07061421B1 Flash ADC with variable LSB 失效
标题翻译：具有可变LSB的闪存ADC
公开(公告)号：US07061421B1
公开(公告)日：2006-06-13
申请号：US11096163
申请日：2005-03-31
申请人： Jinwen Xiao , Ka Y. Leung , Douglas R. Holberg
发明人： Jinwen Xiao , Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M1/78
CPC分类号： H03M1/363 , H02M3/33592 , Y02B70/1475
摘要： A differential analog-to-digital data converter (ADC) is disclosed for receiving a positive input signal and a negative input signal. A distributed resistive device is provided having taps associated therewith. A plurality of comparators each having a signal input and a reference input are provided, the signal input connected to one of the positive and negative input signals and the reference input connected to a tap on said distributed resistive device. A driver drives current through the distributed resistive device with one of the taps of the distributed resistive device disposed at substantially the other of the positive and negative input signals. A current varying device varys the current through the distributed resistive device to vary the voltage between taps.
摘要翻译：公开了用于接收正输入信号和负输入信号的差分模数转换器（ADC）。提供具有与其相关联的抽头的分布式电阻装置。提供了各自具有信号输入和参考输入的多个比较器，所述信号输入连接到正输入信号和负输入信号中的一个以及连接到所述分布式电阻装置上的抽头的基准输入。驱动器驱动电流通过分布式电阻器件，分布式电阻器件的抽头中的一个位于基本上正负输入信号的另一个处。电流变化的装置通过分布式电阻装置改变电流以改变抽头之间的电压。

13. 发明授权

US06384763B1 Segemented D/A converter with enhanced dynamic range 有权
标题翻译：具有增强动态范围的分段D / A转换器
公开(公告)号：US06384763B1
公开(公告)日：2002-05-07
申请号：US09583341
申请日：2000-05-31
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M178
CPC分类号： H03M1/0602 , H03M1/682 , H03M1/765
摘要： A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.
摘要翻译：具有串联连接的晶体管的数模转换器形成用于各个分段电阻串的高阻抗电流源。形成用于一个电阻器串的电流吸收器的串联晶体管通过利用负反馈放大器呈现高输出阻抗。通过使用适当的增益电阻配置输出放大器，可以消除一个电阻串中的裕量电阻和偏移电阻的影响。通过使用相同值的主电阻和子电阻串的所有电阻，可以实现高精度的D / A转换。

14. 发明授权

US07256611B2 Cross-bar matrix with LCD functionality 失效
标题翻译：带有LCD功能的横杆矩阵
公开(公告)号：US07256611B2
公开(公告)日：2007-08-14
申请号：US11005700
申请日：2004-12-07
申请人： Douglas R. Holberg , Kenneth W. Fernald
发明人： Douglas R. Holberg , Kenneth W. Fernald
IPC分类号： H03K19/177
CPC分类号： H03K19/1731
摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.
摘要翻译：交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个单元由控制输入。

15. 发明授权

US06288661B1 A/D converter with voltage/charge scaling 有权
标题翻译：具有电压/电荷缩放的A / D转换器
公开(公告)号：US06288661B1
公开(公告)日：2001-09-11
申请号：US09419148
申请日：1999-10-15
申请人： Douglas R. Holberg
发明人： Douglas R. Holberg
IPC分类号： H03M166
CPC分类号： H03M1/682 , H03M1/46 , H03M1/765
摘要： An analog-to-digital converter having a digital-to-analog converter section for converting a Z-bit digital word. The digital-to-analog converter section includes an MSB portion for receiving a predetermined portion of the upper most significant bits, M bits, of the digital word and providing a monotonic division, VINC, of a reference voltage to provide a first analog voltage. A SubDAC portion is provided for receiving the remaining portion of the digital word, N bits, and providing a monotonic division of the voltage VINC to provide a second analog voltage. A summing device sums the first analog voltage with the second analog voltage to provide an analog output voltage with an M+N bit resolution, Z=M+N.
摘要翻译：一种具有用于转换Z位数字字的数模转换器部分的模数转换器。数模转换器部分包括MSB部分，用于接收数字字的最高有效位M位的预定部分，并提供参考电压的单调除法VINC以提供第一模拟电压。提供SubDAC部分用于接收数字字的剩余部分N位，并且提供电压VINC的单调除法以提供第二模拟电压。求和装置将第一模拟电压与第二模拟电压相加，以提供具有M + N位分辨率的模拟输出电压，Z = M + N。

16. 发明授权

US07382181B2 Method and apparatus for tuning GMC filter 有权
标题翻译： GMC滤波器调谐方法及装置
公开(公告)号：US07382181B2
公开(公告)日：2008-06-03
申请号：US11623686
申请日：2007-01-16
申请人： Golam R. Chowdhury , Douglas R. Holberg
发明人： Golam R. Chowdhury , Douglas R. Holberg
IPC分类号： H03K5/00
CPC分类号： H03H11/04 , H03B5/14 , H03F1/342 , H03F3/45183 , H03F2203/45318 , H03F2203/45366 , H03L7/0995
摘要： A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.
摘要翻译：公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。滤波器的输入使振荡频率调谐到预定频率。

17. 发明授权

US07304679B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US07304679B1
公开(公告)日：2007-12-04
申请号：US10742170
申请日：2003-12-19
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5/222 , H04N5/235 , H04N5/20 , H03M1/12
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

18. 发明授权

US06617934B1 Phase locked loop circuits, systems, and methods 有权
标题翻译：锁相环电路，系统和方法
公开(公告)号：US06617934B1
公开(公告)日：2003-09-09
申请号：US09283098
申请日：1999-03-31
申请人： Douglas R. Holberg , Sandra M. Johnson
发明人： Douglas R. Holberg , Sandra M. Johnson
IPC分类号： H03B524
CPC分类号： H03K3/0322 , H03L7/0995
摘要： A phase locked loop in an imaging system is used to generate signals on one of eight equal phase steps within a clock period. The phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with three inverting stages and one non-inverting stage. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. Differential stages are employed so that the delay of the inverting and non-inverting stage are the same. According to the present invention, the output of the last stage is swapped onto the input of the first stage, making it non-inverting without path delay, permitting oscillation with each stage's output remaining at 45 degrees of the previous stage's phase.
摘要翻译：成像系统中的锁相环用于在时钟周期内的八个相位相位步骤之一上产生信号。锁相环输出8个时钟相位或4个时钟相位及其补码，每个时钟相位以像素速率运行，无需更高速度电路。根据一个实施例，锁相环采用具有三个反相级和一个非反相级的振荡器。在像素时钟速率方面，每个级的输出与前一级的相位相差45度。使用差分级，使得反相和非反相级的延迟相同。根据本发明，最后一级的输出被交换到第一级的输入端上，使其不反相而没有路径延迟，允许每级的输出保持在前一级相位45度的振荡。

19. 发明授权

US6038116A High voltage input pad system 失效
标题翻译：高压输入板系统
公开(公告)号：US6038116A
公开(公告)日：2000-03-14
申请号：US75449
申请日：1998-05-08
申请人： Douglas R. Holberg , Nadi R. Itani , David R. Welland
发明人： Douglas R. Holberg , Nadi R. Itani , David R. Welland
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.
摘要翻译：高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。保护系统包括金属栅极晶体管和提供ESD保护的n阱电阻。通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。

20. 发明授权

US4492927A Offset voltage compensation circuit 失效
标题翻译：偏移电压补偿电路
公开(公告)号：US4492927A
公开(公告)日：1985-01-08
申请号：US430446
申请日：1982-09-30
申请人： Douglas R. Holberg
发明人： Douglas R. Holberg
IPC分类号： H04M1/50
CPC分类号： H04M1/505
摘要： A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42, 44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48,76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50,78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58,82). Row and column integrators (64,92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal. Each signal segment comprises a plurality of similar voltage steps having amplitude and polarity determined by the specialized row and column clock signals (SLOPE RATE, SLOPE SIGN). The row and column signals are combined in a summer (68) to produce the DTMF signal.
摘要翻译：双音多频（DTMF）音产生器电路（10）产生被组合以产生DTMF信号的所选频率行和列音调。键板扫描电路（42,44）扫描传统的按钮电话键盘以产生行和列输入信号。行和列基本速率信号由来自外部晶体（12）的参考信号的基本计数器（48,76）产生。行和列积分率信号由也从参考信号导出的积分器计数器（50,78）产生。专门的行和列时钟控制信号（SLOPE RATE，SLOPE SIGN，AUTO ZERO）由时钟发生器（58,82）生成。行和列积分器（64,92）集成参考信号以以行和列积分率信号的速率产生离散电压步长，以产生由信号的每个周期的多个段组成的行和列信号。每个信号段包括具有由专门的行和列时钟信号（SLOPE RATE，SLOPE SIGN）确定的振幅和极性的多个相似的电压阶跃。行和列信号在夏季（68）中组合以产生DTMF信号。

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