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11. 发明授权

US06351793B2 Memory latency compensation 有权
标题翻译：内存延迟补偿
公开(公告)号：US06351793B2
公开(公告)日：2002-02-26
申请号：US09137439
申请日：1998-08-20
申请人： Thomas Henkel
发明人： Thomas Henkel
IPC分类号： G06F1200
CPC分类号： G06F5/16 , G01R31/31919 , G01R31/31921 , G06F5/06
摘要： An impact of a memory latency time on repeat operations with a memory is reduced by providing a repeat start buffer for buffering a beginning of a data sequence to be repeatedly accessed, and a repeat switching unit, connected with the memory and the repeat start buffer, for switching therebetween for accessing the buffered beginning of the data sequence to be repeatedly accessed when the data sequence is to be repeated. In case of jump operations, a further reduction is achieved by providing a first and a second data buffer connectable with the memory for buffering data sequences, and a switching unit, connected with the data buffers for switching therebetween. The memory is accessible for each data buffer during an idle memory accessing time of the other data buffer for buffering a beginning of a data sequence to be accessed successively.
摘要翻译：通过提供用于缓冲重复访问的数据序列的开始的重复启动缓冲器以及与存储器和重复启动缓冲器连接的重复切换单元，减少了存储器等待时间对具有存储器的重复操作的影响，用于在数据序列要被重复时在其间切换用于访问要重复访问的数据序列的缓冲开始。在跳跃操作的情况下，通过提供与存储器可连接的用于缓冲数据序列的第一和第二数据缓冲器以及与数据缓冲器连接以在其间切换的切换单元来实现进一步的减少。在另一数据缓冲器的空闲存储器访问时间期间，每个数据缓冲器可访问存储器，用于缓冲要连续访问的数据序列的开始。

12. 发明授权

US6090542A Process for inhibiting the transcription of genes 失效
标题翻译：抑制基因转录的方法
公开(公告)号：US6090542A
公开(公告)日：2000-07-18
申请号：US530358
申请日：1996-01-22
申请人： Patrick Baeuerle , Thomas Henkel
发明人： Patrick Baeuerle , Thomas Henkel
IPC分类号： C12N15/09 , A61K31/135 , A61K31/22 , A61K31/40 , A61K38/00 , A61K38/55 , A61P43/00 , C07K5/083 , C07K14/47 , C12N9/99 , C12N15/85 , C12Q1/68 , C07H21/04 , C12N15/63 , A61K37/00
CPC分类号： A61K31/22 , A61K31/135 , A61K31/40 , A61K38/55 , C07K14/4703 , C07K5/0808 , C12N15/85 , C12Q1/6897
摘要： Inhibition of the transcription of genes in higher eukaryotic cells by inhibiting the activation of NF-KB, wherein the cells are treated with substances which specifically inhibit the proteolytic degradation of IKB-.alpha. directly or indirectly. Process for screening substances which inhibit NF-KB activation by inhibiting the proteolytic degradation of IKB-.alpha.. Use of the substances for treating pathological conditions which can be traced back to undesirable gene expression controlled by NF-KB.
摘要翻译： PCT No.PCT / EP94 / 01014 Sec。 371日期1996年1月22日 102（e）日期1996年1月22日PCT 1994年3月31日PCT公布。第WO94 / 23045号公报日期1994年10月13日通过抑制NF-κB的活化来抑制高等真核细胞中基因的转录，其中用特异性抑制IKB-α的蛋白水解降解的物质直接或间接地处理细胞。通过抑制IKB-α的蛋白水解降解来筛选抑制NF-κB活化的物质的方法。这些物质用于治疗可追溯到由NF-κB控制的不良基因表达的病理状况。

13. 发明申请

US20120040956A1 INHIBITORS OF HIF-1 PROTEIN ACCUMULATION 审中-公开
标题翻译： HIF-1蛋白质积累的抑制剂
公开(公告)号：US20120040956A1
公开(公告)日：2012-02-16
申请号：US13152365
申请日：2011-06-03
申请人： Philipp WABNITZ , Matthias Gehling , Thomas Henkel , M. Lienhard Schmitz
发明人： Philipp WABNITZ , Matthias Gehling , Thomas Henkel , M. Lienhard Schmitz
IPC分类号： A61K31/343 , A61P7/00 , A61P13/00 , A61P15/00 , A61P1/00 , A61P17/02 , A61P15/02 , A61P27/02 , A61P27/06 , A61P11/00 , A61P9/12 , A61P13/12 , A61P19/02 , A61P29/00 , A61K31/4025
CPC分类号： A61K31/343 , C07D307/93
摘要： The invention relates to cyclopentabenzofuran derivatives for the treatment and/or prophylaxis of angiogenesis-related disorders.
摘要翻译：本发明涉及用于治疗和/或预防血管发生相关疾病的环戊烷并苯并呋喃衍生物。

14. 发明申请

US20110213026A1 EXTRACTS WITH LIVER-X-RECEPTOR MODULATORS, COMPOUNDS AND THEIR USE ESPECIALLY IN WEIGHT CONTROL 审中-公开
标题翻译：与肝脏受体调节剂，化合物及其在体重控制中特别有用的提取物
公开(公告)号：US20110213026A1
公开(公告)日：2011-09-01
申请号：US12673655
申请日：2008-07-29
申请人： Torsten Grothe , Ernst Roemer , Thomas Henkel
发明人： Torsten Grothe , Ernst Roemer , Thomas Henkel
IPC分类号： A61K31/36 , A61K31/09 , C07C43/23 , C07D317/70 , C07D493/04 , A61P3/04
CPC分类号： A61K31/36 , A61K31/085 , A61K31/09 , A61K31/215 , A61K31/222 , A61K31/343 , A61K36/57 , A61K36/79
摘要： The invention relates to the use, or methods (especially with regard to animals, especially human, that are in need of such treatment) comprising the use, of an extract and/or one or more natural compounds from plants or parts of plants, respectively, from a genus selected from the group consisting of Schisandra, Illicium, Kadsura, Steganotaenia and Magnolia, alone or as supplement, as active ingredient in the regulation of body weight and/or fat loss and/or for the management of obesity, either in humans or in animals, to the use of said extract and/or natural compound(s) or mixtures in the manufacture of a pharmaceutical or nutraceutical formulation for the regulation of body weight and/or fat loss and/or for the management of obesity either in humans or in animals. The above extract and/or compound(s) can further be used to reduce one or more adverse metabolic parameters in a subject. The invention relates also to said extract and/or compound(s) for use in the treatment or in the preparation of a medicament for the treatment of obesity, as well as their preparation. It also relates to pharmaceutical or nutraceutical formulations comprising said extract and/or natural compound(s) which are useful in the regulation of body weight and/or fat loss and/or for the management of obesity.
摘要翻译：本发明涉及分别使用来自植物或植物部分的提取物和/或一种或多种天然化合物的用途或方法（特别是关于动物，特别是人类），选自五味子，Illicium，Kadsura，Steganotaenia和Magnolia的属，单独或作为补充作为活性成分，用于调节体重和/或脂肪减少和/或用于肥胖的管理，人或动物使用所述提取物和/或天然化合物或混合物来制造用于调节体重和/或脂肪损失的药物或营养制剂，和/或用于肥胖的管理在人类或动物中。上述提取物和/或化合物还可用于减少受试者中的一种或多种不利代谢参数。本发明还涉及用于治疗或制备用于治疗肥胖症的药物及其制备的所述提取物和/或化合物。它还涉及包含可用于调节体重和/或脂肪减少和/或用于肥胖的管理的所述提取物和/或天然化合物的药物或营养制剂。

15. 发明授权

US07263601B2 Sequencer unit with instruction buffering 有权
标题翻译：具有指令缓冲的定序器单元
公开(公告)号：US07263601B2
公开(公告)日：2007-08-28
申请号：US10890702
申请日：2004-07-14
申请人： Thomas Henkel
发明人： Thomas Henkel
IPC分类号： G06F11/263 , G06F11/28
CPC分类号： G06F9/3836 , G06F9/3824
摘要： A sequencer unit includes a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is required by a certain instruction, a corresponding data read request for fetching said data. Instructions that wait for requested data are buffered in the instruction buffer. The second instruction processing unit is adapted for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate an output data stream.
摘要翻译：定序器单元包括第一指令处理单元，指令缓冲器和第二指令处理单元。第一指令处理单元适于接收和处理指令流，并且在特定指令需要数据的情况下发出用于取出所述数据的相应数据读取请求。等待请求的数据的指令被缓冲在指令缓冲区中。第二指令处理单元适于接收对应于所发出的数据读取请求之一的请求数据，用于将所请求的数据分配给缓冲在指令缓冲器中的相应指令，并且用于处理所述指令以便产生输出数据流。

16. 发明授权

US07216182B2 Shared storage arbitration 失效
标题翻译：共享存储仲裁
公开(公告)号：US07216182B2
公开(公告)日：2007-05-08
申请号：US10825473
申请日：2004-04-15
申请人： Thomas Henkel
发明人： Thomas Henkel
IPC分类号： G06F13/00
CPC分类号： G06F13/1605
摘要： The invention provides an arbitration unit adapted for controlling accesses to a shared storage. The arbitration unit comprises a set of interfaces adapted for connecting a plurality of units with said arbitration unit, wherein outgoing data streams are transmitted from the arbitration unit via respective ones of said interfaces to at least one of said units, and wherein incoming data streams are transmitted from at least one of said units via respective ones of said interfaces to the arbitration unit. A control logic is connected to each of said interfaces, said control logic being adapted for segmenting write data of incoming data streams in order to set up write accesses to said shared storage, for scheduling a sequence of at least one of write and read accesses to said shared storage, and for distributing read data obtained during said read accesses to outgoing data streams.
摘要翻译：本发明提供一种适于控制对共享存储器的访问的仲裁单元。仲裁单元包括适于将多个单元与所述仲裁单元连接的一组接口，其中输出数据流经由相应的所述接口从仲裁单元发送到所述单元中的至少一个，并且其中输入数据流是从至少一个所述单元经由相应的所述接口发送到仲裁单元。控制逻辑连接到每个所述接口，所述控制逻辑适于分段输入数据流的写入数据，以便建立对所述共享存储器的写入访问，以便对写入和读取访问中的至少一个序列进行调度所述共享存储器，并且用于将在所述读取访问期间获得的读取数据分发到输出数据流。

17. 发明申请

US20050050302A1 Sequencer unit with instruction buffering 有权
标题翻译：具有指令缓冲的定序器单元
公开(公告)号：US20050050302A1
公开(公告)日：2005-03-03
申请号：US10890702
申请日：2004-07-14
申请人： Thomas Henkel
发明人： Thomas Henkel
IPC分类号： G05B19/05 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/3824
摘要： A sequencer unit according to embodiments of the present invention comprises a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is required by a certain instruction, a corresponding data read request for fetching said data. Instructions that wait for requested data are buffered in the instruction buffer. The second instruction processing unit is adapted for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate an output data stream.
摘要翻译：根据本发明的实施例的定序器单元包括第一指令处理单元，指令缓冲器和第二指令处理单元。第一指令处理单元适于接收和处理指令流，并且在特定指令需要数据的情况下发出用于取出所述数据的相应数据读取请求。等待请求的数据的指令被缓冲在指令缓冲区中。第二指令处理单元适于接收对应于所发出的数据读取请求之一的请求数据，用于将所请求的数据分配给缓冲在指令缓冲器中的相应指令，并且用于处理所述指令以便产生输出数据流。

18. 发明授权

US06304947B1 Optimized memory organization in a multi-channel architecture 有权
标题翻译：在多通道架构中优化内存组织
公开(公告)号：US06304947B1
公开(公告)日：2001-10-16
申请号：US09140427
申请日：1998-08-26
申请人： Ralf Killig , Thomas Henkel
发明人： Ralf Killig , Thomas Henkel
IPC分类号： G06F1200
CPC分类号： G01R31/31908 , G01R31/31919
摘要： Described is a computer system having a multi-channel architecture wherein a plurality of individual channels, each having a respective channel memory and being connected by a bus. According to the invention, loading data, and preferably sequential data, into a channel memory of one of the plurality of individual channels is accomplished by (a) loading data into the channel memory to be loaded; (b) distributing further data which is to be loaded into the channel memory to be loaded into another channel memory of another one of the plurality of individual channels; and (c) reloading the data from the channel memory of the other one of the plurality of individual channels to the channel memory to be loaded via the bus. The invention is preferably used in a testing system, such as an IC tester.
摘要翻译：描述了具有多通道架构的计算机系统，其中多个单独的通道，每个通道具有相应的通道存储器并且通过总线连接。根据本发明，通过（a）将数据加载到要加载的通道存储器中来实现将数据加载，并且优选地顺序数据加入到多个单独通道之一的通道存储器中; （b）将要加载到信道存储器中的另外的数据分配以加载到多个单独信道中的另一个的另一个信道存储器中; 以及（c）将数据从多个独立通道中的另一个的通道存储器重新加载到通过总线加载的通道存储器。本发明优选用于诸如IC测试仪的测试系统中。

19. 发明授权

US5499248A Test vector generator comprising a decompression control unit and a conditional vector processing unit and method for generating a test vector 失效
标题翻译：测试矢量发生器，包括解压缩控制单元和用于产生测试向量的条件向量处理单元和方法
公开(公告)号：US5499248A
公开(公告)日：1996-03-12
申请号：US189200
申请日：1994-01-31
申请人： Klaus-Peter Behrens , Martin Fischer , Thomas Henkel
发明人： Klaus-Peter Behrens , Martin Fischer , Thomas Henkel
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/319 , G11C29/56
CPC分类号： G11C29/56 , G01R31/31921 , G01R31/31813 , G01R31/31926
摘要： An apparatus for testing an electronic device, in particular an integrated circuit tester and specifically designed for testing memories or logic/memory combinations, provides a multiplicity of pin channels. Each pin channel includes a sequence controller communicating with a decompression control unit. This combination is extremely fast and allows to designate the respective pin channels to an address or a data pin of a memory or to a logic pin of a device under test. A central controller provides the necessary control instructions to instruction memories of the sequence controllers. All sequence controllers assigned to a logic pin execute basically the same program, wherein pin adaptation is performed by a vector memory. In contrast, sequencers assigned to an address pin execute different, pin-specific instructions. The architecture may be easily adapted to varying pin definitions and is based on the "per pin resource" approach. It may also be applied to board testers and other electronic testing devices.
摘要翻译：用于测试电子设备的装置，特别是用于测试存储器或逻辑/存储器组合的专门设计的集成电路测试器，提供多个引脚通道。每个引脚通道包括与减压控制单元通信的序列控制器。这种组合非常快，并允许将相应的引脚通道指定到存储器的地址或数据引脚或被测器件的逻辑引脚。中央控制器为序列控制器的指令存储器提供必要的控制指令。分配给逻辑引脚的所有序列控制器基本上执行相同的程序，其中引脚适配由向量存储器执行。相比之下，分配给地址引脚的顺控程序会执行不同的引脚特定指令。该架构可以容易地适应于不同的引脚定义，并且基于“每引脚资源”方法。它也可以应用于电路板测试仪和其他电子测试设备。

20. 发明授权

US5492896A Pseudopeptides having an antiviral action 失效
标题翻译：具有抗病毒作用的假肽
公开(公告)号：US5492896A
公开(公告)日：1996-02-20
申请号：US196939
申请日：1994-02-15
申请人： Dieter Habich , Michael Matzke , Klaus Frobel , Thomas Henkel , Hartwig Muller , Karl-Heinz Weber , Jurgen Reefschlager , Gert Streissle , Jutta Hansen , Rainer Neumann , Arnold Paessens
发明人： Dieter Habich , Michael Matzke , Klaus Frobel , Thomas Henkel , Hartwig Muller , Karl-Heinz Weber , Jurgen Reefschlager , Gert Streissle , Jutta Hansen , Rainer Neumann , Arnold Paessens
IPC分类号： A61K38/00 , A61P31/12 , C07K1/02 , C07K1/113 , C07K5/02 , C07K5/06 , C07K5/072 , C07K5/08 , C07K5/09 , C07K14/81 , C07K5/00 , C07K7/00 , C07K17/00
CPC分类号： C07K5/0817 , C07K5/0217 , C07K5/06095 , A61K38/00
摘要： The invention relates to new pseudopeptides having an antiviral action, oft he general formula (I) ##STR1## with the meanings given in the description for the substituents, to a process for their preparation and to their use as antiviral agents, in particular against cytomegaloviruses.
摘要翻译：本发明涉及具有抗病毒作用的新的假肽，其通式（I）为取代基，其制备方法及其作为抗病毒剂，特别是针对巨细胞病毒的用途。

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