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11. 发明授权

US07132360B2 Method for treating a semiconductor surface to form a metal-containing layer 有权
标题翻译：用于处理半导体表面以形成含金属层的方法
公开(公告)号：US07132360B2
公开(公告)日：2006-11-07
申请号：US10865268
申请日：2004-06-10
申请人： James K. Schaeffer , Darrell Roan , Dina H. Triyoso , Olubunmi O. Adetutu
发明人： James K. Schaeffer , Darrell Roan , Dina H. Triyoso , Olubunmi O. Adetutu
IPC分类号： H01L21/4763 , H01L21/8344 , H01L21/8242 , H01L21/336
CPC分类号： H01L21/02181 , C23C16/0272 , H01L21/3141 , H01L21/31645
摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.
摘要翻译：一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。一种或多种金属增强成核以用于随后的材料生长。在已经处理的半导体衬底的暴露表面上形成含金属层。半导体衬底的暴露表面的处理有助于含金属层的聚结。在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。

12. 发明授权

US06686282B1 Plated metal transistor gate and method of formation 有权
标题翻译：镀金属晶体管栅极和形成方法
公开(公告)号：US06686282B1
公开(公告)日：2004-02-03
申请号：US10403967
申请日：2003-03-31
申请人： Cindy Simpson , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Cindy Simpson , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L2144
CPC分类号： H01L21/823842 , H01L21/28079
摘要： Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.
摘要翻译：使用电镀，N沟道和P沟道晶体管的金属栅极由不同的材料形成，以实现这些N和P沟道晶体管的适当的功函数。用与期望层的生长一致的种子层实现电镀。优选的材料选自包含钌，氧化钌，铱，钯，铂，镍，锇和钴的铂金属。这些是有吸引力的金属，因为它们具有相对高的导电性，可以被电镀，并且提供了用于形成P和N沟道晶体管的工作功能的良好选择。

13. 发明授权

US06902969B2 Process for forming dual metal gate structures 有权
标题翻译：双金属门结构形成工艺
公开(公告)号：US06902969B2
公开(公告)日：2005-06-07
申请号：US10632473
申请日：2003-07-31
申请人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
发明人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.
摘要翻译：半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。栅极电介质或蚀刻停止件可以与衬底接触。蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。

14. 发明授权

US07402472B2 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
发明人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

15. 发明授权

US07235502B2 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors 有权
标题翻译：过渡介电层提高高介电常数晶体管的可靠性和性能
公开(公告)号：US07235502B2
公开(公告)日：2007-06-26
申请号：US11096515
申请日：2005-03-31
申请人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L21/31
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译：栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。形成过渡电介质膜（205）可以包括形成多个过渡介电层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。

16. 发明授权

US07144825B2 Multi-layer dielectric containing diffusion barrier material 有权
标题翻译：多层电介质含有扩散阻挡材料
公开(公告)号：US07144825B2
公开(公告)日：2006-12-05
申请号：US10687271
申请日：2003-10-16
申请人： Olubunmi O. Adetutu , Tien Ying Luo , Hsing H. Tseng
发明人： Olubunmi O. Adetutu , Tien Ying Luo , Hsing H. Tseng
IPC分类号： H01L21/00
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.
摘要翻译：公开了形成电介质的方法。该方法包括在半导体材料上形成第一介电层。扩散阻挡材料被引入到第一介电层中。最后，在引入之后，在第一电介质层上形成第二电介质层。

17. 发明授权

US07288458B2 SOI active layer with different surface orientation 有权
公开(公告)号：US07288458B2
公开(公告)日：2007-10-30
申请号：US11302770
申请日：2005-12-14
申请人： Olubunmi O. Adetutu , Robert E. Jones , Ted R. White
发明人： Olubunmi O. Adetutu , Robert E. Jones , Ted R. White
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.

18. 发明授权

US07074664B1 Dual metal gate electrode semiconductor fabrication process and structure thereof 失效
标题翻译：双金属栅电极半导体制造工艺及其结构
公开(公告)号：US07074664B1
公开(公告)日：2006-07-11
申请号：US11092418
申请日：2005-03-29
申请人： Ted R. White , Olubunmi O. Adetutu , Robert E. Jones
发明人： Ted R. White , Olubunmi O. Adetutu , Robert E. Jones
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
摘要翻译：半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。第二栅极电极层形成在第一栅极电极层和栅极电介质上。去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。可以形成第三栅极电极层，覆盖第一和第二栅电极层。第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。

19. 发明授权

US07030001B2 Method for forming a gate electrode having a metal 失效
标题翻译：用于形成具有金属的栅电极的方法
公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
申请人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
发明人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译：一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分未被抑制层覆盖的介电层。

20. 发明授权

US06897095B1 Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode 有权
标题翻译：具有双金属氧化物栅极电介质和单金属栅电极的半导体工艺和集成电路
公开(公告)号：US06897095B1
公开(公告)日：2005-05-24
申请号：US10843850
申请日：2004-05-12
申请人： Olubunmi O. Adetutu , Srikanth B. Samavedam , Bruce E. White
发明人： Olubunmi O. Adetutu , Srikanth B. Samavedam , Bruce E. White
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
摘要翻译：半导体制造工艺包括在第一和第二阱区域分别形成第一和第二晶体管，其中第一晶体管具有第一栅极电介质，而第二晶体管具有不同于第一栅极电介质的第二栅极电介质。第一晶体管具有第一栅电极，第二晶体管具有第二栅电极。第一和第二栅电极的组成相同。第一栅极电介质和第二栅极电介质可以都包括高K电介质，例如氧化铪和氧化铝。第一和第二栅电极都包括覆盖各个栅极电介质的栅极电极层。栅电极层优选为TaSiN和TaC。第一和第二栅电极都可以包括覆盖栅电极层的导电层。在一个这样的实施例中，导电层可以包括多晶硅和钨。

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