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11. 发明授权

US08462577B2 Single transistor driver for address lines in a phase change memory and switch (PCMS) array 有权
标题翻译：单相晶体管驱动器，用于相变存储器和开关（PCMS）阵列中的地址线
公开(公告)号：US08462577B2
公开(公告)日：2013-06-11
申请号：US13051800
申请日：2011-03-18
申请人： Raymond W. Zeng , DerChang Kau
发明人： Raymond W. Zeng , DerChang Kau
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C16/08
摘要： The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.
摘要翻译：本公开涉及非易失性存储器件的制造。在至少一个实施例中，可以使用单个晶体管来驱动每个地址线，字线或位线。可以通过这些单晶体管器件驱动抑制电压和选择电压，这可以通过引入用于地址线的奇数和偶数名称来实现。在一个操作实施例中，可以将所选择的地址线驱动到选择电压，并且允许与所选地址线相同的奇数或偶数指定的地址线浮动。与选择的地址线不同的奇数或偶数名称的地址线被驱动到禁止电压，其中相邻的浮动地址线可以用作到所选地址线的屏蔽线。

12. 发明申请

US20120282752A1 FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS 有权
标题翻译：在相变记忆切换电池中制作电流结构
公开(公告)号：US20120282752A1
公开(公告)日：2012-11-08
申请号：US13553948
申请日：2012-07-20
申请人： Jong Won Lee , DerChang Kau , Gianpaolo Spadini
发明人： Jong Won Lee , DerChang Kau , Gianpaolo Spadini
IPC分类号： H01L21/8239
CPC分类号： H01L45/1675 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.
摘要翻译：在一个或多个实施例中，提供了在相变存储器开关（PCMS）单元中制造电流限制堆叠结构的方法。一个实施例示出了制造具有限制在行和列方向上的上硫属化物中的电流的PCMS电池的方法。在一个实施例中，示出了制造具有亚光刻临界尺度存储硫族化物的PCMS单元的方法。在另一个实施例中，公开了制造具有亚光刻临界尺寸中间电极加热器的PCMS单元的方法。

13. 发明授权

US08184469B2 Stored multi-bit data characterized by multiple-dimensional memory states 有权
标题翻译：以多维存储状态为特征的多位数据存储
公开(公告)号：US08184469B2
公开(公告)日：2012-05-22
申请号：US12627234
申请日：2009-11-30
申请人： Johannes A. Kalb , DerChang Kau , Gianpaolo Spadini
发明人： Johannes A. Kalb , DerChang Kau , Gianpaolo Spadini
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0002 , G11C2013/0052 , G11C2013/0092
摘要： A method for enhancing data storage may comprise storing two or more bits in a memory cell, wherein the stored bits may be characterized by two or more independent variables based, at least in part, on physical properties of the memory cell.
摘要翻译：用于增强数据存储的方法可以包括在存储器单元中存储两个或多个位，其中存储的位可以由至少部分地基于存储单元的物理特性的两个或多个独立变量来表征。

14. 发明授权

US09287498B2 Dielectric thin film on electrodes for resistance change memory devices 有权
标题翻译：用于电阻变化存储器件的电极上的介电薄膜
公开(公告)号：US09287498B2
公开(公告)日：2016-03-15
申请号：US13993302
申请日：2011-09-14
申请人： DerChang Kau
发明人： DerChang Kau
IPC分类号： H01L47/00 , H01L29/04 , H01L21/06 , H01L21/331 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1293 , H01L45/141 , H01L45/16
摘要： Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于增加电阻变化存储器件（也称为相变存储器（PCM））器件中的热绝缘的技术和配置。在一个实施例中，一种装置包括PCM装置的存储结构，所述存储结构具有硫族化物材料，具有导电材料的电极，所述电极具有与所述存储结构直接耦合的第一表面，以及电介质膜具有电介质材料，所述电介质膜与所述电极的与所述第一表面相对设置的第二表面直接耦合。可以描述和/或要求保护其他实施例。

15. 发明授权

US09245926B2 Apparatuses and methods including memory access in cross point memory 有权
公开(公告)号：US09245926B2
公开(公告)日：2016-01-26
申请号：US13465579
申请日：2012-05-07
申请人： DerChang Kau , Gianpaolo Spadini
发明人： DerChang Kau , Gianpaolo Spadini
IPC分类号： G11C11/00 , H01L27/24 , H01L45/00 , G11C13/00 , G11C16/08 , G11C16/24
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.

16. 发明授权

US08605531B2 Fast verify for phase change memory with switch 有权
标题翻译：用开关快速验证相变存储器
公开(公告)号：US08605531B2
公开(公告)日：2013-12-10
申请号：US13163916
申请日：2011-06-20
申请人： DerChang Kau
发明人： DerChang Kau
IPC分类号： G11C7/04
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2213/76
摘要： A phase change memory with switch (PCMS) compensates for threshold voltage drift by utilizing a lower demarcation voltage for a verify operation after programming than for a read operation occurring at least a predetermined period of time after the programming operation.
摘要翻译：具有开关（PCMS）的相变存储器通过利用用于编程之后的验证操作的下分界电压来补偿阈值电压漂移，而不是在编程操作之后至少预定的一段时间内发生的读操作。

17. 发明申请

US20120320670A1 FAST VERIFY FOR PHASE CHANGE MEMORY WITH SWITCH 有权
标题翻译：快速更新用于切换开关的相位存储器
公开(公告)号：US20120320670A1
公开(公告)日：2012-12-20
申请号：US13163916
申请日：2011-06-20
申请人： DerChang Kau
发明人： DerChang Kau
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2213/76
摘要： A phase change memory with switch (PCMS) compensates for threshold voltage drift by utilizing a lower demarcation voltage for a verify operation after programming than for a read operation occurring at least a predetermined period of time after the programming operation.
摘要翻译：具有开关（PCMS）的相变存储器通过利用用于编程之后的验证操作的下分界电压来补偿阈值电压漂移，而不是在编程操作之后至少预定的一段时间内发生的读操作。

18. 发明授权

US08049197B2 Self-aligned nano-cross-point phase change memory 有权
标题翻译：自对准纳米交叉点相变存储器
公开(公告)号：US08049197B2
公开(公告)日：2011-11-01
申请号：US12346702
申请日：2008-12-30
申请人： DerChang Kau
发明人： DerChang Kau
IPC分类号： H01L29/04
CPC分类号： H01L45/1691 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/126 , H01L45/144 , Y10S438/90
摘要： One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.
摘要翻译：一个实施例是一种相变存储器，其包括与相变材料的存储元件横向接触的加热器元件。特别地，存储元件的端部接触加热器元件的端部。第一对电介质间隔物定位在第一加热器元件的相对侧上，第二对电介质间隔物定位在第一存储元件的相对侧上。存储元件，加热器元件以及第一和第二对电介质间隔物可以通过间隔物图案化技术制成。

19. 发明申请

US20100163832A1 SELF-ALIGNED NANO-CROSS-POINT PHASE CHANGE MEMORY 有权
标题翻译：自对准的纳米相位变化记忆
公开(公告)号：US20100163832A1
公开(公告)日：2010-07-01
申请号：US12346702
申请日：2008-12-30
申请人： DerChang Kau
发明人： DerChang Kau
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/1691 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/126 , H01L45/144 , Y10S438/90
摘要： One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.
摘要翻译：一个实施例是一种相变存储器，其包括与相变材料的存储元件横向接触的加热器元件。特别地，存储元件的端部接触加热器元件的端部。第一对电介质间隔物定位在第一加热器元件的相对侧上，第二对电介质间隔物定位在第一存储元件的相对侧上。存储元件，加热器元件以及第一和第二对电介质间隔物可以通过间隔物图案化技术制成。

20. 发明授权

US06911695B2 Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain 有权
标题翻译：晶体管在栅极侧壁上具有绝缘间隔物，以减少源极和漏极的栅极和掺杂延伸区域之间的重叠
公开(公告)号：US06911695B2
公开(公告)日：2005-06-28
申请号：US10247027
申请日：2002-09-19
申请人： Shafqat Ahmed , Henry Chao , DerChang Kau
发明人： Shafqat Ahmed , Henry Chao , DerChang Kau
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7836
摘要： A transistor comprising a gate, a channel beneath the gate and separated from the gate by an insulator, a source adjacent to the channel on a first side of the gate, a drain adjacent to the channel on a second side of the gate, doped extension regions into the channel from the source and the drain that underlap the gate, and insulating spacers adjacent to sidewalls of the gate that overlap the extension regions. The insulating spacers may be used to align the doped extension regions, offset the extension regions from the gate, and reduce Miller capacitance and standby leakage current.
摘要翻译：一种晶体管，包括栅极，栅极下方的沟道，并通过绝缘体与栅极分离，源极与栅极第一侧上的沟道相邻，漏极与栅极第二侧上的沟道相邻，掺杂延伸区域从源极和漏极引入到沟道中，并且与栅极的与延伸区域重叠的侧壁相邻的绝缘间隔物。可以使用绝缘间隔物来对准掺杂的延伸区域，使得延伸区域偏离栅极，并且减小米勒电容和待机漏电流。

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