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11. 发明授权

US5966026A Output buffer with improved tolerance to overvoltage 失效
标题翻译：输出缓冲器，具有改善的过压容差
公开(公告)号：US5966026A
公开(公告)日：1999-10-12
申请号：US738598
申请日：1996-10-29
申请人： Hamid Partovi , Matthew P. Crowley
发明人： Hamid Partovi , Matthew P. Crowley
IPC分类号： G05F1/571 , G05F3/24 , H03K19/0185
CPC分类号： G05F1/571 , G05F3/24 , G05F3/242
摘要： An output buffer with improved tolerance to overvoltage conditions. Among other features, especially when in a high-impedance state, the output buffer prevents a leakage path from a pad (108) through a pull-up driver (101) to supply voltage VDD when any voltage above VDD is placed on the pad (108). Further, the output buffer provides improved transient response characteristics. In one embodiment, the output buffer includes a pull-up driver (101), a first tracking transistor (120), a second tracking transistor (122), a voltage bias generator (112), and a coupling capacitor (124).
摘要翻译：输出缓冲器，具有改善的过电压条件容限。尤其是当处于高阻抗状态时，输出缓冲器防止当焊盘（108）上的任何电压放置在焊盘上时从焊盘（108）穿过上拉驱动器（101）的漏电路径供给电压VDD 108）。此外，输出缓冲器提供改进的瞬态响应特性。在一个实施例中，输出缓冲器包括上拉驱动器（101），第一跟踪晶体管（120），第二跟踪晶体管（122），电压偏置发生器（112）和耦合电容器（124）。

12. 发明授权

US08618856B1 Shadow latch 有权
标题翻译：阴影闩锁
公开(公告)号：US08618856B1
公开(公告)日：2013-12-31
申请号：US13077949
申请日：2011-03-31
申请人： Alfred Yeung , Hamid Partovi , John Ngai , Ronen Cohen
发明人： Alfred Yeung , Hamid Partovi , John Ngai , Ronen Cohen
IPC分类号： H03K3/289
CPC分类号： H03K3/013 , H03K3/356121
摘要： A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.
摘要翻译：闩锁装置设置有驱动器和阴影闩锁。驱动器具有接受二进制驱动器输入信号的输入端，接受时钟信号的输入端和接收阴影Q信号的输入端。驱动器具有响应于驱动器输入信号，阴影-Q信号和时钟信号而提供等于驱动器输入信号的倒数的二进制Q信号的输出。阴影锁存器具有接受驱动器输入信号的输入端和接受时钟信号的输入端。阴影锁存器具有响应于驱动器输入信号和时钟信号而提供等于反相Q信号的阴影Q信号的输出。

13. 发明授权

US07480358B2 CDR-based clock synthesis 有权
标题翻译：基于CDR的时钟合成
公开(公告)号：US07480358B2
公开(公告)日：2009-01-20
申请号：US10786879
申请日：2004-02-25
申请人： Hamid Partovi , William P. Evans
发明人： Hamid Partovi , William P. Evans
IPC分类号： H04L7/00
CPC分类号： H03L7/06 , H04L7/0091
摘要： A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.
摘要翻译：可以通过对具有已知转换密度的潜在噪声时钟源信号执行时钟和数据恢复（CDR）操作来合成时钟信号。 CDR操作响应于时钟源信号产生期望的时钟信号。为了减少串行数据收发器的同步接收和发送时钟域之间的串扰，使用单个公共PLL来从接收到的数据恢复接收时钟，并从潜在的噪声发射时钟源信号合成发送时钟。

14. 发明申请

US20080024215A1 Data sampler including a first stage and a second stage 失效
标题翻译：数据采样器包括第一级和第二级
公开(公告)号：US20080024215A1
公开(公告)日：2008-01-31
申请号：US11494848
申请日：2006-07-28
申请人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
发明人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译：数据采样器，包括第一级和第二级。第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

15. 发明申请

US20070180281A1 Electrical idle detection circuit including input signal rectifier 有权
标题翻译：电气怠速检测电路包括输入信号整流器
公开(公告)号：US20070180281A1
公开(公告)日：2007-08-02
申请号：US11346064
申请日：2006-02-02
申请人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
发明人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
IPC分类号： G06F1/32
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译：一种包括全波整流器和第一放大器的电怠速检测电路。全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。

16. 发明授权

US06440839B1 Selective air gap insulation 有权
标题翻译：选择性气隙绝缘
公开(公告)号：US06440839B1
公开(公告)日：2002-08-27
申请号：US09639800
申请日：2000-08-17
申请人： Hamid Partovi , Chun Jiang , Bill Yowjuang Liu
发明人： Hamid Partovi , Chun Jiang , Bill Yowjuang Liu
IPC分类号： H01L21768
CPC分类号： H01L21/7682
摘要： Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.
摘要翻译：气隙绝缘区选择性地形成在其中导电线紧密接近的高寄生电容区域内，并产生不可容忍的寄生电容量。选择性地形成气隙绝缘区域通过减小常规气隙绝缘方案的应力断裂问题，通过减小寄生电容和器件可靠性来提高电路性能。

17. 发明授权

US06087872A Dynamic latch circuitry 失效
标题翻译：动态锁存电路
公开(公告)号：US06087872A
公开(公告)日：2000-07-11
申请号：US28960
申请日：1998-02-23
申请人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi Di Gregorio , Donald A. Draper
发明人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi Di Gregorio , Donald A. Draper
IPC分类号： H03K3/12
CPC分类号： H03K3/12
摘要： A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.
摘要翻译：高性能动态触发电路实现。动态触发器电路包括“隐式”单触发以产生延迟时钟输出（319）。触发器包括耦合到时钟输入（305）的延迟块（317）。触发器可以是D型触发器。在触发器的正边沿触发实施例中，延迟时钟输出（319）的下降沿（440）在延迟时段（448）之后的时钟信号的上升沿（444）之后。触发器响应于在该延迟时段（448）期间的时钟输入（310）在数据输入（305）处的新数据中进行时钟。数据保存在存储块（360）中。触发器具有非常好的瞬态特性，特别是设置和时钟到输出时间。触发器不消耗静电。

18. 发明授权

US5964884A Self-timed pulse control circuit 失效
标题翻译：自定时脉冲控制电路
公开(公告)号：US5964884A
公开(公告)日：1999-10-12
申请号：US938589
申请日：1997-09-26
申请人： Hamid Partovi , John Christian Holst , Amos Ben-Meir
发明人： Hamid Partovi , John Christian Holst , Amos Ben-Meir
IPC分类号： G06F12/10 , G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/412 , G11C11/418 , G11C29/02 , G11C29/18 , G11C29/32 , G11C29/50 , H03K3/356 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/099 , G06F1/04
CPC分类号： G11C29/026 , G06F12/1054 , G11C11/4087 , G11C11/412 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , H03K3/356156 , H03K5/13 , H03L7/08 , G11C11/401 , G11C11/41 , G11C16/04 , G11C17/14 , G11C2029/5004 , G11C2029/5006 , H03K2005/00019 , H03K2005/00071 , H03L7/0995
摘要： A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.
摘要翻译：自定时脉冲控制电路和操作方法非常适用于调整定时电路的延迟以防止逻辑比赛。在说明性示例中，STPC电路用于调整自定时读出放大器中的定时。自定时脉冲控制（STPC）电路与使用STPC调整的定时结构定时的电路结构集成在集成电路芯片上。 STPC还有利地用于修改时钟的占空比，确定关键定时路径，从而优化整个电路速度，并调整动态电路定时，使不可操作的电路变得有用。

19. 发明授权

US5774005A Latching methodology 失效
标题翻译：闭锁方法
公开(公告)号：US5774005A
公开(公告)日：1998-06-30
申请号：US706340
申请日：1996-08-30
申请人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi DiGregorio , Donald A. Draper
发明人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi DiGregorio , Donald A. Draper
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.
摘要翻译：高性能触发电路实现。触发器电路包括“隐式”单触发以产生延迟的时钟输出（407）。触发器包括耦合到时钟输入（210）的延迟块（405）。触发器可以是D型触发器。在触发器的正边沿触发实施例中，延迟时钟输出（407）的下降沿（540）在延迟时段（548）之后的时钟信号的上升沿（544）之后。触发器响应于在该延迟时段（548）期间的时钟输入（210）在数据输入端（205）处的新数据中的时钟。数据保存在存储块（450）中。触发器具有非常好的瞬态特性，特别是设置和时钟到输出时间。触发器不消耗静电。

20. 发明授权

US5487025A Carry chain adder using regenerative push-pull differential logic 失效
标题翻译：携带加法器使用再生推挽差分逻辑
公开(公告)号：US5487025A
公开(公告)日：1996-01-23
申请号：US152561
申请日：1993-11-15
申请人： Hamid Partovi , Donald A. Draper
发明人： Hamid Partovi , Donald A. Draper
IPC分类号： G06F7/50 , G06F7/503 , H03K19/017
CPC分类号： G06F7/503 , G06F7/507 , H03K19/01742 , G06F2207/3872
摘要： A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition of a second plurality of bits together with a carry from the addition of the first plurality of bits results in a carry, and a second carry chain circuit selectively generates a second carry-out signal indicating whether the addition of the second plurality of bits without a carry from the addition of the first plurality of bits results in a carry. Selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, selects either the first carry-out signal or the second carry-out signal in response to the carry-in signal. The first and second carry chain circuits and/or the selection circuitry each includes a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential. Altering circuitry is provided for altering the voltage potential at the first and second nodes for causing the first and second transistors to be in a conducting state and for accelerating the voltage at the first and second nodes to final voltage potentials.
摘要翻译：进位指示电路选择性地产生指示第一多个位的相加是否导致进位的进位信号。第一进位链电路选择性地产生第一进位输出信号，该第一进位输出信号指示从第一多个位的相加中是否添加第二多个位与进位一起导致进位，并且第二进位链电路选择性地产生指示是否从第一多个比特的添加中添加没有进位的第二多个比特导致携带。耦合到进位指示电路和第一和第二进位链电路的选择电路响应于输入信号选择第一进位信号或第二进位输出信号。第一和第二进位链电路和/或选择电路各自包括连接到第二晶体管的第一晶体管，使得当第一节点处于第一电压电位时，第一和第二进位链电路和/或选择电路可以被初始偏置为非导通状态，第二节点处于第二电压电位，第一电压电位不同于第二电压电位。提供改变电路用于改变第一和第二节点处的电压电位，以使第一和第二晶体管处于导通状态并用于将第一和第二节点处的电压加速到最终电压电位。

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