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11. 发明申请

US20050006242A1 Void-free damascene copper deposition process and means of monitoring thereof 失效
标题翻译：无空隙镶嵌铜沉积工艺及其监控手段
公开(公告)号：US20050006242A1
公开(公告)日：2005-01-13
申请号：US10615794
申请日：2003-07-10
申请人： Panayotis Andricacos , Dean Chung , Hariklia Deligianni , James Fluegel , Keith Kwietniak , Peter Locke , Darryl Restaino , Soon-Cheon Seo , Philippe Vereecken , Erick Walton
发明人： Panayotis Andricacos , Dean Chung , Hariklia Deligianni , James Fluegel , Keith Kwietniak , Peter Locke , Darryl Restaino , Soon-Cheon Seo , Philippe Vereecken , Erick Walton
IPC分类号： C23C18/16 , C25D21/12 , C25D21/18
CPC分类号： C23C18/1617 , C23C18/1683 , C25D21/12 , C25D21/18
摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.
摘要翻译：公开了一种稳定湿化学浴的改进方法。通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。特别地，本发明涉及镀铜浴。更具体地说，本发明涉及镀铜浴的稳定性。更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。

12. 发明授权

US5872694A Method and apparatus for determining wafer warpage for optimized electrostatic chuck clamping voltage 失效
标题翻译：用于确定优化的静电卡盘夹紧电压的晶片翘曲的方法和装置
公开(公告)号：US5872694A
公开(公告)日：1999-02-16
申请号：US996576
申请日：1997-12-23
申请人： Mark Hoinkis , Darryl Restaino
发明人： Mark Hoinkis , Darryl Restaino
IPC分类号： B65G49/07 , B25J15/06 , H01L21/683 , H02N13/00
CPC分类号： H01L21/6831 , H02N13/00
摘要： Method and apparatus are provided for determining a warpage of a wafer (14) for providing a minimum clamping voltage to an electrostatic chuck (ESC) when the wafer is subsequently processed thereon. The apparatus includes an electrostatic chuck (12, 120) and a control arrangement (16, 18, 20). The electrostatic chuck includes a clamping surface (13, 130) for clamping a wafer thereto by a clamping force that is dependent on a clamping voltage applied to the electrostatic chuck. The control arrangement is used to detect an inherent warpage in the wafer prior to a processing of that wafer, and determine a minimum clamping voltage from the measured warpage that is to be applied to the electrostatic chuck during a subsequent processing of the wafer. The minimum clamping voltage has a value for each wafer that securely clamps the wafer to the clamping surface and avoids excessive warpage and backside abrasion of the wafer. The control arrangement includes a suitable wafer warpage measuring tool (20, 50, 52, 54) such as, for example, a capacitance warpage measuring tool (50, 52, 54) or a optical warpage measuring tool (20) that measures the inherent warpage of a wafer, and an electrostatic chuck software control (18). The electrostatic chuck software control uses the measured warpages to determine and store data of a minimum clamping voltages and an associated wafer identification for each wafer for use in subsequently processing each wafer.
摘要翻译：提供了用于确定晶片（14）的翘曲的方法和装置，用于当晶片随后在其上处理时，向静电卡盘（ESC）提供最小钳位电压。该装置包括静电吸盘（12,120）和控制装置（16,18,20）。静电卡盘包括用于通过取决于施加到静电卡盘的夹紧电压的夹紧力将晶片夹紧到其上的夹紧表面（13,130）。控制装置用于在该晶片的处理之前检测晶片中的固有翘曲，并且在随后的晶片处理期间从测量的翘曲确定最小钳位电压。每个晶片的最小钳位电压具有将晶片牢固地夹持在夹紧表面上并避免晶片过度翘曲和背面磨损的值。控制装置包括合适的晶片翘曲测量工具（20,50,52,54），例如电容翘曲测量工具（50,52,54）或光学翘曲测量工具（20），其测量固有的晶片的翘曲和静电卡盘软件控制（18）。静电卡盘软件控制使用测量的扭曲来确定和存储每个晶片的最小钳位电压和相关晶片标识的数据，以用于随后处理每个晶片。

13. 发明申请

US20070148958A1 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US20070148958A1
公开(公告)日：2007-06-28
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

14. 发明申请

US20060202311A1 LOW k DIELECTRIC CVD FILM FORMATION PROCESS WITH IN-SITU IMBEDDED NANOLAYERS TO IMPROVE MECHANICAL PROPERTIES 有权
标题翻译：低k电介质CVD薄膜形成工艺，具有改善机械性能的现场纳米复合纳米粒子
公开(公告)号：US20060202311A1
公开(公告)日：2006-09-14
申请号：US10906815
申请日：2005-03-08
申请人： Son Nguyen , Sarah Lane , Eric Liniger , Kensaku Ida , Darryl Restaino
发明人： Son Nguyen , Sarah Lane , Eric Liniger , Kensaku Ida , Darryl Restaino
IPC分类号： H01L23/58 , H01L21/469 , H01L23/52
CPC分类号： H01L21/76801 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3105 , H01L21/31633 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.
摘要翻译：具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k电介质材料和存在于至少一个低k电介质材料内的至少一个纳米层。

15. 发明申请

US20050230831A1 Structure to improve adhesion between top CVD low-k dielectiric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低k介电层和介电顶盖层之间的粘附
公开(公告)号：US20050230831A1
公开(公告)日：2005-10-20
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

16. 发明申请

US20050087490A1 Process for removing impurities from low dielectric constant films disposed on semiconductor devices 审中-公开
标题翻译：从设置在半导体器件上的低介电常数膜除去杂质的工艺
公开(公告)号：US20050087490A1
公开(公告)日：2005-04-28
申请号：US10695374
申请日：2003-10-28
申请人： Mark Chace , Jeffrey Hedrick , Habib Hichri , Keith Pope , Jia Lee , Kelly Malone , Kenneth McCullough , Wayne Moreau , Darryl Restaino , Shahab Siddiqui
发明人： Mark Chace , Jeffrey Hedrick , Habib Hichri , Keith Pope , Jia Lee , Kelly Malone , Kenneth McCullough , Wayne Moreau , Darryl Restaino , Shahab Siddiqui
IPC分类号： B01D11/04 , B01D11/00
CPC分类号： B01D11/0407
摘要： A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.
摘要翻译：从设置在半导体器件上的固化的低介电常数有机聚合物膜去除杂质的方法。该方法包括将低介电常数可固化有机聚合物膜设置在半导体器件的导电表面上。有机聚合物膜在半导体器件上固化，随后与超临界二氧化碳接触，任选地在至少一种助溶剂的存在下。

17. 发明申请

US20050059258A1 Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same 有权
标题翻译：具有改善SiCOH电介质界面强度的结构及其制备方法
公开(公告)号：US20050059258A1
公开(公告)日：2005-03-17
申请号：US10662022
申请日：2003-09-12
申请人： Daniel Edelstein , Alfred Grill , Vishnubhai Patel , Darryl Restaino
发明人： Daniel Edelstein , Alfred Grill , Vishnubhai Patel , Darryl Restaino
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02274 , H01L21/02315 , H01L21/3122 , H01L21/31633 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.
摘要翻译：半导体器件结构和制造方法包括具有顶部第一层的衬底; 位于所述第一层顶部的第二薄过渡层; 以及位于所述过渡层顶部的第三层，其中所述第二薄过渡层在所述结构的所述第一和第三层之间提供强粘合力和内聚强度。此外，半导体器件结构和制造方法包括绝缘结构，其包括多个介电层和导电层，其中设置有各自的过渡键合层以增强不同层之间的界面强度。此外，电子器件结构包括绝缘和导电材料层，作为后端线（“BEOL”）布线结构中的层间或层间电介质，其中不同对的介电膜之间的界面强度由薄的中间过渡粘合层。

18. 发明授权

US5798301A Method of manufacturing metal interconnect structure for an integrated circuit with improved electromigration reliability 失效
标题翻译：制造具有改善的电迁移可靠性的集成电路的金属互连结构的方法
公开(公告)号：US5798301A
公开(公告)日：1998-08-25
申请号：US841030
申请日：1997-04-29
申请人： Pei-Ing Paul Lee , Bernd Vollmer , Darryl Restaino , Bill Klaasen
发明人： Pei-Ing Paul Lee , Bernd Vollmer , Darryl Restaino , Bill Klaasen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76843 , H01L21/28512 , H01L21/7685 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.
摘要翻译：一种用于半导体集成电路的多层互连结构，包括钛基底层，第二氮化钛层，第三层铝合金和顶层氮化钛。包含在多层互连结构内的所有层通过原位沉积沉积在超高真空沉积系统中。沉积在沉积系统中的不同层连续进行，而不会破坏真空。尽管多层互连结构中的每个层都沉积在具有多个沉积室的集成超高真空沉积系统内，但不同层的沉积在不同的温度下进行。通过在超过300℃，优选350℃至550℃的温度下沉积铝合金层，由铝合金的电迁移引起的多层互连结构的电迁移故障的时间大大增加。 C.在铝合金层下面的钛层和相邻的氮化钛层提供具有低电阻率的互连结构并防止基底衬底的合金尖峰。结果，提供了具有改善的电迁移可靠性和低电阻的多层互连结构，从而使集成电路内的应用更加密集。

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