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11. 发明申请

US20070046389A1 Reduced cross-talk signaling circuit and method 失效
标题翻译：减少串扰信号电路和方法
公开(公告)号：US20070046389A1
公开(公告)日：2007-03-01
申请号：US11209549
申请日：2005-08-23
申请人： Daniel Dreps , Anand Haridass , Bao Truong , Joel Ziegelbein
发明人： Daniel Dreps , Anand Haridass , Bao Truong , Joel Ziegelbein
IPC分类号： H01P5/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.
摘要翻译：两个或多个IC之间的信令使用信令方案，其中在驱动器侧和接收机侧产生参考信号。驱动器侧参考信号通过形成参考通道的传输线路通道耦合到接收机侧参考信号。数据信号通道与每两个相邻数据通道之间的参考通道配对。相邻的数据信号通道对都分开一个空的布线通道。成对的数据信号在差分接收机的一个输入端被接收。两个成对数据信道之间的参考信道的参考信号耦合到两个差分接收机的另一个输入端。从配对数据通道耦合到参考通道出现共模噪声，并被差分接收器拒绝。信道数量从全差分信令方案中减少。

12. 发明申请

US20060184817A1 Elastic interface de-skew mechanism 有权
标题翻译：弹性界面去歪斜机制
公开(公告)号：US20060184817A1
公开(公告)日：2006-08-17
申请号：US11055866
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： G06F1/04
CPC分类号： G06F5/06 , G06F1/10
摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.
摘要翻译：用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。

13. 发明申请

US20060182215A1 Dynamic recalibration mechanism for elastic interface 失效
标题翻译：弹性界面的动态重新校准机制
公开(公告)号：US20060182215A1
公开(公告)日：2006-08-17
申请号：US11055865
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： H04L7/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over and elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wraparound eye tracking.
摘要翻译：公开了一种用于使接收到的数字数据进行偏斜和对准的弹性接口总线的方法和装置。在接收到数据后，通过可编程延迟线发送。在可编程延迟线中，数据在数据眼图中的三个点进行采样。动态调整三个采样点，以最大化数据眼图的覆盖范围。在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在主采样器中的延迟调整时从功能采样器采样。在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。该方法和装置允许替代眼睛跟踪和环绕眼睛跟踪。

14. 发明申请

US20060181337A1 Digitally tunable high-current current reference with high PSRR 失效
标题翻译：数字可调高电流电流参考，高PSRR
公开(公告)号：US20060181337A1
公开(公告)日：2006-08-17
申请号：US11055840
申请日：2005-02-11
申请人： Daniel Dreps , Norman James , Hector Saenz
发明人： Daniel Dreps , Norman James , Hector Saenz
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple digitally selectable inputs are included in the current reference circuit and are coupled to the current source circuit. These inputs are used to adjust a value of the current reference output.
摘要翻译：公开了一种数字可调低电压CMOS电流参考。提供了一种可调谐电流参考电路，其包括耦合到电源电压的电流源电路。电流源电路提供稳定的电流参考输出，而不管电源电压的波动。多个数字可选输入包括在当前参考电路中并耦合到电流源电路。这些输入用于调整当前参考输出的值。

15. 发明申请

US20080098149A1 SIGNAL HISTORY CONTROLLED SLEW-RATE TRANSMISSION METHOD AND BUS INTERFACE TRANSMITTER 失效
标题翻译：信号历史控制的单向传输方法和总线接口发射机
公开(公告)号：US20080098149A1
公开(公告)日：2008-04-24
申请号：US11962093
申请日：2007-12-21
申请人： Daniel De Araujo , Daniel Dreps , Bhyrav Mutnury
发明人： Daniel De Araujo , Daniel Dreps , Bhyrav Mutnury
IPC分类号： G06F13/00 , H03K5/12
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译：信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。

16. 发明申请

US20060181324A1 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US20060181324A1
公开(公告)日：2006-08-17
申请号：US11215416
申请日：2005-08-30
申请人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
发明人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

17. 发明申请

US20060164059A1 On-chip high frequency power supply noise sensor 有权
标题翻译：片上高频电源噪声传感器
公开(公告)号：US20060164059A1
公开(公告)日：2006-07-27
申请号：US11040225
申请日：2005-01-21
申请人： Daniel Dreps , Seongwon Kim , Michael Sperling
发明人： Daniel Dreps , Seongwon Kim , Michael Sperling
IPC分类号： G05F3/04 , G05F3/08
CPC分类号： H03K5/08 , G01R19/16552 , G01R29/26
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。这具有以不需要校准的方式直接感测电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

18. 发明申请

US20060033646A1 Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry 有权
公开(公告)号：US20060033646A1
公开(公告)日：2006-02-16
申请号：US10896504
申请日：2004-07-22
申请人： Daniel Dreps , Robert Reese , Hector Saenz
发明人： Daniel Dreps , Robert Reese , Hector Saenz
IPC分类号： H03M7/00
CPC分类号： H04L25/03866 , H04L7/0008
摘要： Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

19. 发明申请

US20050007145A1 Thevenins receiver 失效
公开(公告)号：US20050007145A1
公开(公告)日：2005-01-13
申请号：US10616845
申请日：2003-07-10
申请人： Daniel Dreps , Frank Ferraiolo , Anand Haridass , Bao Truong
发明人： Daniel Dreps , Frank Ferraiolo , Anand Haridass , Bao Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

20. 发明申请

US20070195572A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE 有权
标题翻译： 276引脚缓冲存储器模块，具有增强的故障容限
公开(公告)号：US20070195572A1
公开(公告)日：2007-08-23
申请号：US11735640
申请日：2007-04-16
申请人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Mark Kellogg , Roger Rippens
发明人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Mark Kellogg , Roger Rippens
IPC分类号： G11C5/06
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a pluality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译：双列直插式存储器模块（DIMM）包括具有约151.2至约151.5毫米的长度的卡，连接到该卡的各个本地存储器件的抽头以及附接到该卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡片包括至少276个配置在其上的针脚。

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